Datasheet

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ADS58B18

ADS58B19

www.ti.com

SBAS487D – NOVEMBER 2009–REVISED JANUARY 2011

11-Bit, 200MSPS/9-Bit, 250MSPS,

Ultralow-Power ADCs with Analog Buffer

Check for Samples: ADS58B18, ADS58B19

FEATURES

DESCRIPTION

• ADS58B18: 11-Bit, 200MSPS

The ADS58B18/B19 are members of the ultralow

power ADS4xxx analog-to-digital converter (ADC)

• ADS58B19: 9-Bit, 250MSPS

family that features integrated analog buffers and

• Integrated High-Impedance Analog Input

SNRBoost technology. The ADS58B18 and

Buffer

ADS58B19 are 11-bit and 9-bit ADCs with sampling

• Ultralow Power:

rates up to 200MSPS and 250MSPS, respectively.

Innovative design techniques are used to achieve

– Analog Power: 258mW at 200MSPS

high dynamic performance while consuming

– I/O Power: 69mW (DDR LVDS, low LVDS

extremely low power. The analog input pins have

swing)

buffers with constant performance and input

• High Dynamic Performance:

impedance across a wide frequency range. This

architecture makes these parts well-suited for

– ADS58B18: 66dBFS SNR and 81dBc SFDR

multi-carrier, wide bandwidth communications

at 150MHz

applications such as PA linearization.

– ADS58B19: 55.7dBFS SNR and 76dBc

The ADS58B18 uses TI-proprietary SNRBoost

SFDR at 150MHz

technology that can be used to overcome SNR

• Enhanced SNR Using TI-Proprietary SNRBoost

limitation as a result of quantization noise for

Technology (ADS58B18 Only)

bandwidths less than Nyquist (f

/2).

– –77.7dBFS SNR in 20MHz Bandwidth

Both devices have gain options that can be used to

• Dynamic Power Scaling with Sample Rate

improve SFDR performance at lower full-scale input

• Output Interface:

ranges, especially at very high input frequencies.

They also include a dc offset correction loop that can

– Double Data Rate (DDR) LVDS with

be used to cancel the ADC offset. At lower sampling

Programmable Swing and Strength

rates, the ADC automatically operates at scaled-down

– Standard Swing: 350mV

power with no loss in performance.

– Low Swing: 200mV

These devices support both double data rate (DDR)

– Default Strength: 100Ω Termination

low-voltage differential signaling (LVDS) and parallel

– 2x Strength: 50Ω Termination

CMOS digital output interfaces. The low data rate of

the DDR LVDS interface (maximum 500Mbps) makes

– 1.8V Parallel CMOS Interface Also

it possible to use low-cost field-programmable gate

Supported

array (FPGA)-based receivers. They have a

• Programmable Gain for SNR/SFDR Trade-Off

low-swing LVDS mode that can be used to further

• DC Offset Correction

reduce the power consumption. The strength of the

LVDS output buffers can also be increased to support

• Supports Low Input Clock Amplitude

50Ω differential termination.

• Package: QFN-48 (7mm × 7mm)

The ADS58B18/B19 are both available in a compact

QFN-48 package and specified over the industrial

temperature range (–40°C to +85°C).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments Incorporated.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (69 pages)

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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com 11-Bit, 200MSPS/9-Bit, 250MSPS, Ultralow-Power ADCs with Analog Buffer Check for Samples: ADS58B18, ADS58B19 FEATURES DESCRIPTION • • • The ADS58B18/B19 are members of the ultralow power ADS4xxx analog-to-digital converter (ADC) family that features integrated analog buffers and SNRBoost technology. The ADS58B18 and ADS58B19 are 11-bit and 9-bit ADCs with sampling rates up to 200MSPS and 250MSPS, respectively.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS ADS58B18, ADS58B19 MIN TYP MAX UNIT 1.7 1.8 1.9 V 3 3.3 3.6 V 1.7 1.8 1.9 V SUPPLIES AVDD Analog supply voltage AVDD_BUF Analog buffer supply voltage DRVDD Digital supply voltage ANALOG INPUTS Differential input voltage range 1.5 VPP 1.7 ± 0.05 V Maximum analog input frequency with 1.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com ELECTRICAL CHARACTERISTICS: ADS58B18/ADS58B19 Typical values are at +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, 50% clock duty cycle, –1dBFS differential analog input, and DDR LVDS interface, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.8V.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com ELECTRICAL CHARACTERISTICS: GENERAL Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, 50% clock duty cycle, and 0dB gain, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.8V. ADS58B18 PARAMETER MIN TYP ADS58B19 MAX MIN TYP MAX UNIT ANALOG INPUTS Differential input voltage range 1.5 1.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com DIGITAL CHARACTERISTICS The dc specifications refer to the condition where the digital outputs are not switching but are permanently at a valid logic level '0' or '1'. AVDD = 1.8V and DRVDD = 1.8V.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com ADS58B18, ADS58B19 Pin Assignments (LVDS Mode) (continued) PIN NAME PIN NUMBER # OF PINS FUNCTION DESCRIPTION OE 7 1 I Output buffer enable input, active high; this pin has an internal 180kΩ pull-up resistor to DRVDD. DFS 6 1 I Data format select input. This pin sets the DATA FORMAT (twos compliment or offset binary) and the LVDS/CMOS output interface type. See Table 4 for detailed information.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com ADS58B18, ADS58B19 Pin Assignments (CMOS Mode) (continued) PIN NAME PIN NUMBER # OF PINS FUNCTION DESCRIPTION DFS 6 1 I Data format select input. This pin sets the DATA FORMAT (twos compliment or offset binary) and the LVDS/CMOS output interface type. See Table 4 for detailed information. SNRBoost_En 23 1 I ADS58B18: Digital control pin for SNRBoost mode, active high. ADS58B19: Unused.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAMS AVDD AGND DRVDD DDR LVDS Interface DRGND CLKP CLKOUTP CLOCKGEN CLKOUTM CLKM D0_P D0_M D1_D2_P AVDD_BUF D1_D2_M D3_D4_P INP 14-Bit ADC Sampling Circuit Digital Functions SNRBoost DDR Serializer D3_D4_M D5_D6_P INM D5_D6_M D7_D8_P Analog Buffers D7_D8_M Control Interface Reference VCM D9_D10_P D9_D10_M OVR_SDOUT OE SNRBoost_En DFS SEN SDATA SCLK RESET ADS58B18 Figure 5.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 AVDD www.ti.com AGND DRVDD DDR LVDS Interface DRGND CLKP CLKOUTP CLOCKGEN CLKOUTM CLKM D0_P AVDD_BUF D0_M D1_D2_P INP D1_D2_M 9-Bit ADC Sampling Circuit DDR Serializer Digital Functions INM D3_D4_P D3_D4_M D5_D6_P Analog Buffers D5_D6_M Control Interface Reference VCM D7_D8_P D7_D8_M OVR_SDOUT OE DFS SEN SDATA SCLK RESET ADS58B19 Figure 6.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com TIMING CHARACTERISTICS Dn_Dn + 1_P Logic 0 VOD = -350mV Logic 1 VOD = +350mV Dn_Dn + 1_M VOCM GND (1) With external 100Ω termination. Figure 7. LVDS Output Voltage Levels TIMING REQUIREMENTS: LVDS and CMOS Modes (1) Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, sampling frequency = 250 MSPS, sine wave input clock, CLOAD = 5pF (2), and RLOAD = 100Ω (3), unless otherwise noted.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com TIMING REQUIREMENTS: LVDS and CMOS Modes(1) (continued) Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, sampling frequency = 250 MSPS, sine wave input clock, CLOAD = 5pF(2), and RLOAD = 100Ω(3), unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.7V to 1.9V.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Table 1. LVDS Timing Across Sampling Frequencies SAMPLING FREQUENCY (MSPS) SETUP TIME (ns) MIN TYP 230 0.85 200 1.05 185 HOLD TIME (ns) MAX MIN TYP 1.25 0.35 0.6 1.55 0.35 0.6 1.1 1.7 0.35 0.6 160 1.6 2.1 0.35 0.6 125 2.3 3 0.35 0.6 80 4.5 5.2 0.35 0.6 MAX Table 2.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com CLKM Input Clock CLKP tPDI CLKOUTP Output Clock CLKOUTM tSU Output Dn_Dn + 1_P Data Pair Dn_Dn + 1_M tSU tH Dn (1) Dn + 1 tH (1) (1) Dn = bits D0, D2, D4, etc. Dn + 1 = Bits D1, D3, D5, etc. Figure 9. LVDS Mode Timing CLKM Input Clock CLKP tPDI Output Clock CLKOUT tSU Output Data Dn tH Dn (1) CLKM Input Clock CLKP tSTART tDV Output Data Dn Dn (1) Dn = bits D0, D1, D2, etc. Figure 10.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com DEVICE CONFIGURATION The ADS58B18/9 have several modes that can be configured using a serial programming interface, as described in Table 4 through Table 7. In addition, the devices have three dedicated parallel pins for quickly configuring commonly-used functions. The parallel pins are DFS (analog 4-level control pin), OE (digital control pin), and SNRBoost_En (digital control pin).
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com SERIAL INTERFACE The analog-to-digital converter (ADC) has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), and SDATA (serial interface data) pins.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Serial Register Readout The device includes a mode where the contents of the internal registers can be read back on the OVR_SDOUT pin. This readback may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. After power-up and device reset, the OVR_SDOUT pin functions as an over-range indicator pin by default.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com SERIAL REGISTER MAP Table 8 summarizes the functions supported by the serial interface. Table 8.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com DESCRIPTION OF SERIAL REGISTERS Register Address 00h (Default = 00h) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 RESET READOUT Bits[7:2] Always write '0' Bit 1 RESET: Software reset applied This bit resets all internal registers to the default values and self-clears to 0 (default = 1). Bit 0 READOUT: Serial readout This bit sets the serial readout of the registers.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Register Address 25h (Default = 00h) 7 6 5 4 GAIN Bits[7:4] 3 2 1 0 0 TEST PATTERNS GAIN: Gain programmability These bits set the gain programmability in 0.5dB steps. 0000 0110 0111 1000 1001 1010 1011 1100 = = = = = = = = 0dB gain (default after reset) 0.5dB gain 1dB gain 1.5dB gain 2dB gain 2.5dB gain 3dB gain 3.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Register Address 3Dh (Default = 00h) 7 6 DATA FORMAT Bits[7:6] 5 4 ENABLE OFFSET CORR SNRBoost Enable 3 2 1 0 SNRBoost Coeff1 DATA FORMAT: Data format selection These bits select the data format. 00 = The DFS pin controls data format selection 10 = Twos complement 11 = Offset binary Bit 5 ENABLE OFFSET CORR: Offset correction setting This bit sets the offset correction.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Register Address 41h (Default = 00h) 7 6 LVDS CMOS Bits[7:6] 5 4 CMOS CLKOUT STRENGTH 3 ENABLE CLKOUT RISE 2 1 CLKOUT RISE POSN 0 ENABLE CLKOUT FALL LVDS CMOS: Interface selection These bits select the interface. 00 = The DFS pin controls the selection of either LVDS or CMOS interface 01 = DDR LVDS interface 11 = Parallel CMOS interface Bits[5:4] CMOS CLKOUT STRENGTH Controls strength of CMOS output clock only.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Register Address 42h (Default = 00h) 7 6 CLKOUT FALL POSN Bits[7:6] 5 0 4 3 2 1 0 0 DIS LOW LATENCY STBY 0 BYTE-WISE En CLKOUT FALL POSN These bits control the position of the output clock falling edge.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Register Address 43h (Default = 00h) 7 6 5 4 3 2 1 0 PDN GLOBAL 0 PDN OBUF 0 0 EN LVDS SWING Bit 7 Always write '0' Bit 6 PDN GLOBAL: Power-down 0 This bit sets the state of operation. 0 = Normal operation 1 = Total power down; the ADC, internal references, and output buffers are powered down; slow wake-up time. Bit 5 Always write '0' Bit 4 PDN OBUF: Power-down output buffer This bit set the output buffer.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Register Address CFh (Default = 00h) 7 6 FREEZE OFFSET CORR 0 Bit 7 5 4 3 2 OFFSET CORR TIME CONSTANT 1 0 0 0 FREEZE OFFSET CORR This bit sets the freeze offset correction. 0 = Estimation of offset correction is not frozen (bit ENABLE OFFSET CORR must be set). 1 = Estimation of offset correction is frozen (bit EN OFFSET CORR must be set).
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Register Address DFh (Default = 00h) 7 6 0 0 5 4 LOW SPEED Bits[7:6] Always write '0' Bits[5:4] LOW SPEED: Low-speed mode 3 2 1 0 0 0 0 0 00, 01, 10 = Low-speed mode disabled (default state after reset); this setting is recommended for sampling rates greater than 80MSPS. 11 = Low-speed mode enabled; this setting is recommended for sampling rates lower than or equal to 80MSPS.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS58B18 At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. FFT FOR 20MHz INPUT SIGNAL FFT FOR 170MHz INPUT SIGNAL 0 0 SFDR = 92.8dBc SNR = 66.1dBFS SINAD = 66.1dBFS THD = 89.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS58B18 (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS58B18 (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS58B18 (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS58B18 (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. PERFORMANCE ACROSS INPUT AMPLITUDE 66 84 SFDR SNR 65.4 78 SFDR (dBc, dBFS) 65.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS58B18 (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS58B19 At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. FFT FOR 20MHz INPUT SIGNAL FFT FOR 170MHz INPUT SIGNAL 0 0 SFDR = 75.8dBc SNR = 55.7dBFS SINAD = 55.7dBFS THD = 84.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS58B19 (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. SNR ACROSS INPUT FREQUENCY 80 57 75 56.5 70 56 SNR (dBFS) SFDR (dBc) SFDR ACROSS INPUT FREQUENCY 65 55.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS58B19 (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS58B19 (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. PERFORMANCE ACROSS INPUT COMMON-MODE VOLTAGE 58 SFDR SNR 57 74 56.5 72 56 70 55.5 68 55 66 54.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS58B19 (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS: GENERAL At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com APPLICATION INFORMATION THEORY OF OPERATION The ADS58B18 and ADS58B19 are members of the ultralow power ADS4xxx analog-to-digital converter (ADC) family with integrated analog buffers and SNRBoost technology. The analog-to-digital conversion process is initiated by a rising edge of the external input clock when the analog input signal is sampled.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Drive Circuit Requirements The primary advantage of the buffered analog inputs is the isolation of the external drive source from the switching currents of the sampling circuit. The filtering of the glitches with an external R-C-R filter, as suggested for the ADS4149 family, is not required. Using a simple drive circuit, it is possible to obtain uniform performance over a wide frequency range.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Driving Circuit Two example driving circuit configurations are shown in Figure 61 and Figure 62—one optimized for low input frequencies and the other optimized for high input frequencies. Notice in both cases that the board circuitry is simplified compared to the non-buffered ADS4149. In Figure 61, a single transformer is used and is suited for low input frequencies.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com CLOCK INPUT The ADS58B18/19 clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance. The common-mode voltage of the clock inputs is set to VCM using internal 5kΩ resistors. This setting allows the use of transformer-coupled drive circuits for sine-wave clock or ac-coupling for LVPECL and LVDS clock sources.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com SNR ENHANCEMENT USING SNRBoost (ADS58B18 ONLY) SNRBoost technology makes it possible to overcome SNR limitations resulting from quantization noise. Using SNRBoost, enhanced SNR can be obtained for any bandwidth (less than Nyquist or fS/2; see Table 4). SNR improvement is achieved without affecting the default harmonic performance. SNRBoost can be enabled using the SNRBoost_EN pin or via register bits.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Table 9 shows the relation between each coefficient and its corner frequency. By choosing appropriate coefficients, the bathtub can be positioned over the frequency range of 0 to fS/2 (Table 10 shows some examples). By positioning the bathtub within the desired signal band, SNR improvement can be achieved (see Table 4). Note that as the bandwidth is increased, the amount of SNR improvement reduces.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com GAIN FOR SFDR/SNR TRADE-OFF The ADS58B18/19 include gain settings that can be used to get improved SFDR performance. The gain is programmable from 0dB to 3.5dB (in 0.5dB steps) using the GAIN register bits. For each gain setting, the analog input full-scale range scales proportionally, as shown in Table 11. The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades approximately between 0.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com OFFSET CORRECTION The ADS58B18/19 has an internal offset corretion algorithm that estimates and corrects dc offset up to ±10mV. The correction can be enabled using the ENABLE OFFSET CORR serial register bit. Once enabled, the algorithm estimates the channel offset and applies the correction every clock cycle. The time constant of the correction loop is a function of the sampling clock frequency.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com POWER DOWN The ADS58B18/19 has three power-down modes: power-down global, standby, and output buffer disable. Power-Down Global In this mode, the entire chip (including the ADC, internal reference, and the output buffers) are powered down, resulting in reduced total power dissipation of about 10mW. The output buffers are in a high-impedance state.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com DDR LVDS Outputs In this mode, the data bits and clock are output using low voltage differential signal (LVDS) levels. Two data bits are multiplexed and output on each LVDS differential pair, as shown in Figure 67 and Figure 68. Two bit order options are available: bit-wise sequence (default) and byte-wise sequence. Byte-wise sequence can be programmed with the BYTE-WISE En Register bit. Figure 67.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com CLKOUTP CLKOUTM D0_P, D0_M 0 D0 0 D0 D1_D2_P, D1_D2_M D1 D2 D1 D2 D3_D4_P, D3_D4_M D3 D4 D3 D4 D5_D6_P, D5_D6_M D5 D6 D5 D6 D7_D8_P, D7_D8_M D7 D8 D7 D8 D9_D10_P, D9_D10_M D9 D10 D9 D10 Sample N Sample N + 1 (1) Bits D9 and D10 are only available in the ADS58B18. Figure 69.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com CLKOUTP CLKOUTM D0_P, D0_M 0 D4 0 D4 D1_D2_P, D1_D2_M D0 D5 D0 D5 D3_D4_P, D3_D4_M D1 D6 D1 D6 D5_D6_P, D5_D6_M D2 D7 D2 D7 D7_D8_P, D7_D8_M D3 D8 D3 D8 Sample N Sample N + 1 Figure 71. ADS58B19 Byte-Wise Sequence (Only with DDR LVDS Interface) LVDS Output Data and Clock Buffers The equivalent circuit of each LVDS output buffer is shown in Figure 72.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Parallel CMOS Interface In CMOS mode, each data bit is output on a separate pin as the CMOS voltage level, for every clock cycle. The rising edge of the output clock CLKOUT can be used to latch data in the receiver. Figure 73 depicts the CMOS output interface. Switching noise (caused by CMOS output data transitions) can couple into the analog inputs and degrade SNR.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Use External Clock Buffer (> 200MSPS) Input Clock Receiver (FPGA, ASIC, etc.) Flip-Flops CLKOUT CMOS Output Buffers D0 D1 D2 CLKIN D0_In D1_In D2_In 9-/11-Bit ADC Data ADS58B1x Use short traces between ADC output and receiver pins (1 to 2 inches). Figure 74.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Input Over-Voltage Indication (OVR_SDOUT Pin) The device has an OVR_SDOUT pin that provides information about analog input overload (as long as the READOUT register bit is '0'). When the READOUT bit is '1', it functions as a serial readout pin. At any clock cycle, if the sampled input voltage exceeds the positive or negative full-scale range, the OVR pin goes high. The OVR remains high as long as the overload condition persists.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com DEFINITION OF SPECIFICATIONS Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3dB with respect to the low-frequency value. Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. This delay is different across channels.
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com Effective Number of Bits (ENOB) – ENOB is a measure of the converter performance as compared to the theoretical limit based on quantization noise. ENOB = SINAD - 1.76 6.02 (4) Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (PS) to the power of the first nine harmonics (PD). THD = 10Log10 PS PN (5) THD is typically given in units of dBc (dB to carrier).
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ADS58B18 ADS58B19 SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (August 2010) to Revision D Page • Changed documet status to production data ........................................................................................................................ 1 • Updated status of ADS58B19 to production data throughout document ........................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS58B18IRGZR VQFN RGZ 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS58B18IRGZT VQFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS58B19IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS58B18IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 ADS58B18IRGZT VQFN RGZ 48 250 336.6 336.6 28.6 ADS58B19IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 ADS58B19IRGZT VQFN RGZ 48 250 336.6 336.6 28.
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