Datasheet

®
ADS574
8
DESIGNATION DEFINITION FUNCTION
CE (Pin 6) Chip Enable Must be HIGH (“1”) to either initiate a conversion or read output data. 0-1 edge may be used to initiate a
(active high) conversion.
CS (Pin 3) Chip Select Must be LOW (“0”) to either initiate a conversion or read output data. 1-0 edge may be used to initiate a
(active low) conversion.
R/C (Pin 5) Read/Convert Must be LOW (“0”) to initiate either 8- or 12-bit conversions. 1-0 edge may be used to initiate a conversion.
(“1” = read) Must be HIGH (“1”) to read output data. 0-1 edge may be used to initiate a read operation.
(“0” = convert)
A
O
(Pin 4) Byte Address In the start-convert mode, A
O
selects 8-bit (A
O
= “1”) or 12-bit (A
O
= “0”) conversion mode. When reading
Short Cycle output data in two 8-bit bytes, A
O
= “0” accesses 8 MSBs (high byte) and A
O
= “1” accesses 4 LSBs and
trailing “0s” (low byte).
12/8 (Pin 2) Data Mode Select When reading output data, 12/8 = “1” enables all 12 output bits simultaneously. 12/8 = “0” will enable the
(“1” = 12 bits) MSBs or LSBs as determined by the A
O
line.
(“0” = 8 bits)
TABLE II. Control Line Functions.
Binary (BIN) Output Input Voltage Range and LSB Values
Analog Input Voltage Range Defined As: ±10V +5V 0V to +10V 0V to +20V
One Least Significant Bit FSR 20V 10V 10V 20V
(LSB) 2
n
2
n
2
n
2
n
2
n
n = 8 78.13mV 39.06mV 39.06mV 78.13mV
n = 12 4.88mV 2.44mV 2.44mV 4.88mV
Output Transition Values
FFE
H
to FFF
H
+ Full-Scale Calibration +10V – 3/2LSB +5V – 3/2LSB +10V – 3/2LSB +10V – 3/2LSB
7FFF
H
to 800
H
Midscale Calibration (Bipolar Offset) 0 – 1/2LSB 0 – 1/2LSB +5V – 1/2LSB ±10V – 1/2LSB
000
H
to 001
H
Zero Calibration ( – Full-Scale Calibration) –10V + 1/2LSB –5V + 1/2LSB 0 to +1/2LSB 0 to +1/2LSB
TABLE I. Input Voltages, Transition Values, and LSB Values.
CE CS R/C 12/8 A
O
OPERATION
0XXXXNone
X 1 X X X None
0 0 X 0 Initiate 12-bit conversion
0 0 X 1 Initiate 8-bit conversion
1 0 X 0 Initiate 12-bit conversion
1 0 X 1 Initiate 8-bit conversion
1 0 X 0 Initiate 12-bit conversion
1 0 X 1 Initiate 8-bit conversion
1011XEnable 12-bit output
10100Enable 8 MSBs only
10101Enable 4 LSBs plus 4
trailing zeroes
TABLE III. Control Input Truth Table.
↑
↑
↓
↓
↓
↓
READING OUTPUT DATA
After conversion is initiated, the output data buffers remain
in a high-impedance state until the following four logic
conditions are simultaneously met: R/C HIGH, STATUS
LOW, CE HIGH, and CS LOW. Upon satisfaction of these
conditions the data lines are enabled according to the state of
inputs 12/8 and A
0
. See Figure 6 and Table V for timing
relationships and specifications.
In most applications the 12/8 input will be hard-wired in
either the high or low condition, although it is fully TTL and
CMOS-compatible and may be actively driven if desired.
When 12/8 is HIGH, all 12 output lines (DB0-DB11) are
enabled simultaneously for full data word transfer to a 12-bit
or 16-bit bus. In this situation the A
0
state is ignored when
reading the data.
When 12/8 is LOW, the data is presented in the form of two
8-bit bytes, with selection of the byte of interest accom-
plished by the state of A
0
during the read cycle. When A
0
is
LOW, the byte addressed contains the 8MSBs. When A
0
is
HIGH, the byte addressed contains the 4LSBs from the
conversion followed by four logic zeros which have been
forced by the control logic. The left-justified formats of the
two 8-bit bytes are shown in Figure 7. Connection of the
ADS574 to an 8-bit bus for transfer of the data is illustrated
in Figure 8. The design of the ADS574 guarantees that the
A
0
input may be toggled at any time with no damage to the
converter; the outputs which are tied together in Figure 8
cannot be enabled at the same time. The A
0
input is usually
driven by the least significant bit of the address bus, allow-
ing storage of the output data word in two consecutive
memory locations.