Datasheet

®
ADS574
4
CONNECTION DIAGRAM
1
2
3
4
5
Power-Up Reset
Control
Logic
Clock
12 Bits
Succesive Approximation Register
12
Bits
Three-State Buffers and Control
Nibble A
Nibble BNibble C
–
+
CDAC
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+5VDC Supply
(V )
DD
A
O
–
R/C
–
12/8
CE
NC*
2.5V Ref
Out
Analog
Common
2.5V Ref
In
Bipolar
Offset
10V Range
20V Range
Digital
Common
DB0 (LSB)
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11 (MSB)
Status
*Not Internall
y
Connected
2.5V
Reference
CS
V
EE
(Mode Control)