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POWER-SUPPLY SEQUENCE
AVDD
REFP
29
28
2 kW
1 W
1 mF
POWER-DOWN
REFERENCE CIRCUIT
29
30
31
REFP
REFM
IREF
1 W
1 W
56.2 kW
1 mF
1 mF
ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
The preferred power-up sequence is to ramp AV
DD
first, followed by DRV
DD
, including a simultaneous ramp of
AV
DD
and DRV
DD
. In the event that DRV
DD
ramps up first in the system, care must be taken to ensure that AV
DD
ramps up within 10 ms. Optionally, it is recommended to put a 2-k Ω resistor from REFP (pin 29) to AVDD as
shown in Figure 41 . This helps to make the device more robust to power supply ramp-up timings.
Figure 41.
The device enters power-down in one of two ways: either by reducing the clock speed or by setting the PDN bit
throught the serial programming interface. Using the reduced clock speed, power-down may be initiated for clock
frequency below 2 MSPS. The exact frequency at which the power down occurs varies from device to device.
Using the serial interface PDN bit to power down the device places the outputs in a high-impedance state and
only the internal reference remains on to reduce the power-up time. The power-down mode reduces power
dissipation to approximately 180 mW.
The ADS5542 has built-in internal reference generation, requiring no external circuitry on the printed circuit
board (PCB). For optimum performance, it is best to connect both REFP and REFM to ground with a 1- µ F
decoupling capacitor (the 1- Ω resistor shown in Figure 42 is optional). In addition, an external 56.2-k Ω resistor
should be connected from IREF (pin 31) to AGND to set the proper current for the operation of the ADC, as
shown in Figure 42 . No capacitor should be connected between pin 31 and ground; only the 56.2-k Ω resistor
should be used.
Figure 42. REFP, REFM, and IREF Connections for Optimum Performance
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