Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGSsecond and third footnotes to Absolute Maximum Ratings table.
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- DIGITAL CHARACTERISTICS
- TIMING CHARACTERISTICSrows 5 through 15, and footnotes 5 and 6 to Timing Characteristics table.
- RESET TIMING CHARACTERISTICS
- SERIAL PROGRAMMING INTERFACE CHARACTERISTICS
- PIN CONFIGURATION
- DEFINITION OF SPECIFICATIONSthe Definition of Specifications section.
- TYPICAL CHARACTERISTICS
- TYPICAL CHARACTERISTICS
- APPLICATION INFORMATIONInput Voltage Stress section in Applications Information.

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Input Clock
Analog
Input
Signal
Sample
N
N + 1
N + 2
N + 3
N + 4
N + 14
N + 16
N + 17
N + 15
N − 17 N − 16 N − 15 N − 14 N − 13 N − 3 N − 2 N − 1 N
t
su
t
h
t
START
t
A
t
END
t
PDI
Data Out
(D0−D13)
17.5 Clock Cycles
Data Invalid
Output Clock
TIMING CHARACTERISTICS
(1) (2)
Production Data
ADS5541
SBAS307C – MAY 2004 – REVISED FEBRUARY 2007
NOTE: It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above
timing matches closely with the specified values.
Figure 1. Timing Diagram
At T
A
= +25°C, min and max specified over the full temperature range of –40°C to +85°C, sampling rate = 105MSPS, 50%
clock duty cycle, AV
DD
= DRV
DD
= 3.3V, and 3V
PP
differential clock, unless otherwise noted.
ADS5541
PARAMETER DESCRIPTION MIN TYP MAX UNIT
Switching Specification
t
A
Aperture delay Input CLK falling edge to data sampling point 1 ns
Aperture jitter (uncertainty) Uncertainty in sampling instant 300 fs
t
SU
Data setup time Data valid
(3)
to 50% of CLKOUT rising edge 2.2 2.8 ns
t
H
Data hold time 50% of CLKOUT rising edge to data becoming invalid
(3)
2.2 2.5 ns
t
START
(4) (5)
Input clock to output data
Input clock rising edge to data valid start delay 1.9 2.8 ns
valid start
t
END
(4) (5)
Input clock to output data
Input clock rising edge to data valid end delay 5.8 7.3 ns
valid end
t
JIT
Output clock jitter Uncertainty in CLKOUT rising edge, peak-to-peak 175 250 ps
t
RISE
Output clock rise time Rise time of CLKOUT from 20% to 80% of DRV
DD
2 2.2 ns
t
FALL
Output clock fall time Fall time of CLKOUT from 80% to 20% of DRV
DD
1.7 1.8 ns
t
PDI
Input clock to output clock Input clock rising edge, zero crossing, to output clock 4 4.7 5.5 ns
delay rising edge 50%
t
R
Data rise time Data rise time measured from 20% to 80% of DRV
DD
4.4 5.1 ns
t
F
Data fall time Data fall time measured from 80% to 20% of DRV
DD
3.3 3.8 ns
Output enable(OE) to data Time required for outputs to have stable timings with Clock
1000
output delay regard to input clock
(6)
after OE is activated cycles
Time to valid data after coming out of software power Clock
Wakeup time 1000
down and stopping and restarting the clock cycles
Clock
Latency Time for a sample to propagate to the ADC outputs 17.5
cycles
(1) Timing parameters are ensured by design and characterization and not tested in production.
(2) See Table 5 through Table 8 in the Application Information section for timing information at additional sampling frequencies.
(3) Data valid refers to 2V for LOGIC high and 0.8V for LOGIC low.
(4) See the Output Information section for details on using the input clock for data capture.
(5) These specifications apply when the CLKOUT polarity is set to rising edge (according to Table 3 ). Add 1/2 clock period for the valid
number for a falling edge CLKOUT polarity.
(6) Data outputs are available within a clock from assertion of OE; however, it takes 1000 clock cycles to ensure stable timing with respect
to input clock.
6
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