Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGSsecond and third footnotes to Absolute Maximum Ratings table.
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- DIGITAL CHARACTERISTICS
- TIMING CHARACTERISTICSrows 5 through 15, and footnotes 5 and 6 to Timing Characteristics table.
- RESET TIMING CHARACTERISTICS
- SERIAL PROGRAMMING INTERFACE CHARACTERISTICS
- PIN CONFIGURATION
- DEFINITION OF SPECIFICATIONSthe Definition of Specifications section.
- TYPICAL CHARACTERISTICS
- TYPICAL CHARACTERISTICS
- APPLICATION INFORMATIONInput Voltage Stress section in Applications Information.

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CLOCK INPUT
0.01
µ
F
CLKP
CLKM
0.01
µ
F
Differential Square Wave
or Sine Wave
(3V
PP
)
ADS5541
5 kW
5 kW
3 pF 3 pF
6 pF
CLKP
CLKM
CM CM
Clock Duty Cycle (%)
65
70
75
80
85
90
95
40 45 50 55 60
f
IN
= 20MHz
SNR
SFDR
SNR (dBFS) SFDR (dBc)
0.01
µ
F
0.01
µ
F
CLKP
CLKM
Square Wave
or Sine Wave
(3V
PP
)
ADS5541
Production Data
ADS5541
SBAS307C – MAY 2004 – REVISED FEBRUARY 2007
The ADS5541 clock input can also be driven
differentially, reducing susceptibility to
The ADS5541 clock input can be driven with either a
common-mode noise. In this case, it is best to
differential clock signal or a single-ended clock input,
connect both clock inputs to the differential input
with little or no difference in performance between
clock signal with 0.01 µ F capacitors, as shown in
both configurations. The common-mode voltage of
Figure 47 .
the clock inputs is set internally to CM (pin 17) using
internal 5k Ω resistors that connect CLKP (pin 10)
and CLKM (pin 11) to CM (pin 17), as shown in
Figure 45 .
Figure 47. AC-Coupled, Differential Clock Input
For high-input frequency sampling, it is
recommended to use a clock source with low jitter.
Additionally, the internal ADC core uses both edges
of the clock for the conversion process. This means
that, ideally, a 50% duty cycle should be provided.
Figure 48 shows the performance variation of the
ADC versus clock duty cycle.
Figure 45. Clock Inputs
When driven with a single-ended CMOS clock input,
it is best to connect CLKM (pin 11) to ground with a
0.01 µ F capacitor, while CLKP is ac-coupled with a
0.01 µ F capacitor to the clock source, as shown in
Figure 46 .
Figure 48. AC Performance vs Clock Duty Cycle
Figure 46. AC-Coupled, Single-Ended Clock Input
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