Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) Internal HTQFP 64

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FEATURES DESCRIPTION

APPLICATIONS

ADS5541

Serial Programming Register

Control Logic

Timing Circuitry

Internal

Reference

Output

Control

CLKOUT

CLK+

CLK−

IN+

IN−

DRV

OVR

DFS

Digital

Error

Correction

14-Bit

Pipeline

ADC

Core

S&H

GND

SCLKSDATASEN

D13

Production Data

ADS5541

SBAS307C – MAY 2004 – REVISED FEBRUARY 2007

14-Bit, 105MSPS

Analog-To-Digital Converter

• 14-Bit Resolution

The ADS5541 is a high-performance, 14-bit,

105MSPS analog-to-digital converter (ADC). To

• 105MSPS Sample Rate

provide a complete converter solution, it includes a

• High SNR: 72dBFS at 100MHz f

high-bandwidth linear sample-and-hold stage (S&H)

• High SFDR: 86dBc at 100MHz f

and internal reference. Designed for applications

• 2.3V

Differential Input Voltage demanding the highest speed and highest dynamic

performance in a small space, the ADS5541 has

• Internal Voltage Reference

excellent analog power dissipation of 571mW at 3.3V

• 3.3V Single-Supply Voltage

single-supply voltage. This allows an even higher

• Analog Power Dissipation: 571mW

system integration density. The provided internal

reference simplifies system design requirements.

• Serial Programming Interface

The parallel CMOS compatible outputs ensure

• TQFP-64 PowerPAD™ Package

seamless interfacing with common logic.

• Pin-Compatible With:

The ADS5541 is available in a TQFP-64 PowerPAD

– ADS5500 (14-Bit, 125MSPS)

package over the industrial temperature range.

– ADS5542 (14-Bit, 80MSPS)

ADS5500 PRODUCT FAMILY

– ADS5520 (12-Bit, 125MSPS)

80MSPS 105MSPS 125MSPS

– ADS5521 (12-Bit, 105MSPS)

12-Bit ADS5522 ADS5521 ADS5542

– ADS5522 (12-Bit, 80MSPS)

14-Bit ADS5542 ADS5541 ADS5500

• Recommended Op Amps:

– OPA695, OPA847, THS3202, THS3201,

THS4503, THS4509, THS9001

• Wireless Communication

– Communication Receivers

– Base Station Infrastructure

• Test and Measurement Instrumentation

• Single and Multichannel Digital Receivers

• Communication Instrumentation

– Radar, Infrared

• Video and Imaging

• Medical Equipment

• Military Equipment

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (36 pages)

PAGE 1
Production Data ADS5541 SBAS307C – MAY 2004 – REVISED FEBRUARY 2007 14-Bit, 105MSPS Analog-To-Digital Converter FEATURES DESCRIPTION • • • • • • • • • • • The ADS5541 is a high-performance, 14-bit, 105MSPS analog-to-digital converter (ADC). To provide a complete converter solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference.
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Production Data ADS5541 www.ti.com SBAS307C – MAY 2004 – REVISED FEBRUARY 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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Production Data ADS5541 www.ti.com SBAS307C – MAY 2004 – REVISED FEBRUARY 2007 RECOMMENDED OPERATING CONDITIONS ADS5541 MIN TYP MAX UNIT Analog supply voltage, AVDD 3 3.3 3.6 V Output driver supply voltage, DRVDD 3 3.3 3.6 V 1.45 1.55 Supplies Analog Input Differential input range 2.3 Input common-mode voltage, VCM (1) VPP 1.
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Production Data ADS5541 www.ti.com SBAS307C – MAY 2004 – REVISED FEBRUARY 2007 ELECTRICAL CHARACTERISTICS (continued) At TA = +25°C, min and max specified over the full temperature range of –40°C to +85°C, AVDD = DRVDD = 3.3V, sampling rate = 105MSPS, 50% clock duty cycle, DLL On, 3VPP differential clock, and –1dBFS differential input, unless otherwise noted. ADS5541 PARAMETER CONDITIONS MIN TYP MAX UNIT Dynamic AC Characteristics fIN = 10MHz fIN = 55MHz Signal-to-noise ratio. SNR 73.
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Production Data ADS5541 www.ti.com SBAS307C – MAY 2004 – REVISED FEBRUARY 2007 ELECTRICAL CHARACTERISTICS (continued) At TA = +25°C, min and max specified over the full temperature range of –40°C to +85°C, AVDD = DRVDD = 3.3V, sampling rate = 105MSPS, 50% clock duty cycle, DLL On, 3VPP differential clock, and –1dBFS differential input, unless otherwise noted. ADS5541 PARAMETER CONDITIONS MIN TYP MAX UNIT Dynamic AC Characteristics (continued) f = 10.1MHz, 15.
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Production Data ADS5541 www.ti.com SBAS307C – MAY 2004 – REVISED FEBRUARY 2007 Analog Input Signal Sample N N + 1 N + 2 N + 3 N + 4 N + 14 N + 15 N + 16 N + 17 tA Input Clock tSTART Output Clock tPDI tsu Data Out (D0−D13) N − 17 N − 16 N − 15 tEND N − 14 N − 13 N−3 N−2 N−1 N Data Invalid th 17.5 Clock Cycles NOTE: It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above timing matches closely with the specified values.
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Production Data ADS5541 www.ti.com SBAS307C – MAY 2004 – REVISED FEBRUARY 2007 Power Supply (AVDD, DRVDD) t1 10 ms t2 2 ms t3 2 ms SEN Active RESET (Pin 35) Figure 2. Reset Timing Diagram RESET TIMING CHARACTERISTICS Typical values given at TA = +25°C, min and max specified over the full temperature range of –40°C to +85°C, AVDD = DRVDD = 3.3V, and 3VPP differential clock, unless otherwise noted.
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Production Data ADS5541 www.ti.com SBAS307C – MAY 2004 – REVISED FEBRUARY 2007 SERIAL PROGRAMMING INTERFACE CHARACTERISTICS The ADS5541 has a three-wire serial interface. The device latches the serial data SDATA on the falling edge of serial clock SCLK when SEN is active. • Serial shift of bits is enabled when SEN is low. SCLK shifts serial data at the falling edge. • Minimum width of data stream for a valid loading is 16 clocks. • Data is loaded at every 16th SCLK falling edge while SEN is low.
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Production Data ADS5541 www.ti.com SBAS307C – MAY 2004 – REVISED FEBRUARY 2007 Table 2. Serial Register Table A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 (1) D0 DLL CTRL DESCRIPTION Clock DLL 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Internal DLL is on; recommended for 60MSPS to 105MSPS clock speeds. 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 Internal DLL is off; recommended for 2MSPS to 80MSPS clock speeds.
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Production Data ADS5541 www.ti.
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Production Data ADS5541 www.ti.com SBAS307C – MAY 2004 – REVISED FEBRUARY 2007 PIN CONFIGURATION (continued) PIN ASSIGNMENTS (1) TERMINAL NAME NO. NO. OF PINS I/O AVDD 5, 7, 9, 15, 22, 24, 26, 28, 33, 34, 37, 39 12 I Analog power supply AGND 6, 8, 12–14, 16, 18, 21, 23, 25, 27, 32, 36, 38 14 I Analog ground (PowerPAD must be connected to analog ground).
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Production Data ADS5541 www.ti.com SBAS307C – MAY 2004 – REVISED FEBRUARY 2007 DEFINITION OF SPECIFICATIONS Offset Error Analog Bandwidth The analog input frequency at which the power of the fundamental is reduced by 3dB with respect to the low frequency value. The offset error is the difference, given in number of LSBs, between the ADC actual average idle channel output code and the ideal average idle channel output code. This quantity is often mapped into mV.
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Production Data ADS5541 www.ti.com SBAS307C – MAY 2004 – REVISED FEBRUARY 2007 Total Harmonic Distortion (THD) Reference Error THD is the ratio of the power of the fundamental (PS) to the power of the first eight harmonics (PD). P THD + 10Log 10 S PD (4) The reference error is the variation of the actual reference voltage (VREFP – VREFM) from its ideal value. The reference error is typically given as a percentage. THD is typically given in units of dBc (dB to carrier).
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Production Data ADS5541 www.ti.com SBAS307C – MAY 2004 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = DRVDD = 3.3V, sampling rate = 105MSPS, 50% clock duty cycle, DLL On, 3VPP differential clock, and –1dBFS differential input, unless otherwise noted. SPECTRAL PERFORMANCE (FFT for 4MHz Input Signal) 0 0 SFDR = 91.6dBc SNR = 74.3dBFS THD = 87.5dBc SINAD = 74.1dBFS -40 -60 -80 SFDR = 87.3dBc SNR = 73.9dBFS THD = 85.7dBc SINAD = 73.
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Production Data ADS5541 www.ti.com SBAS307C – MAY 2004 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = DRVDD = 3.3V, sampling rate = 105MSPS, 50% clock duty cycle, DLL On, 3VPP differential clock, and –1dBFS differential input, unless otherwise noted. SPECTRAL PERFORMANCE (FFT for 150MHz Input Signal) 0 0 SFDR = 74.3dBc SNR = 71.5dBFS THD = 74.1dBc SINAD = 69.9dBFS SFDR = 73.1dBc SNR = 69.5dBFS THD = 72.
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Production Data ADS5541 www.ti.com SBAS307C – MAY 2004 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = DRVDD = 3.3V, sampling rate = 105MSPS, 50% clock duty cycle, DLL On, 3VPP differential clock, and –1dBFS differential input, unless otherwise noted. DIFFERENTIAL NONLINEARITY INTEGRAL NONLINEARITY 2.0 1.0 fIN = 10 MHz AIN = −0.5 dBFS 0.8 0.6 1.0 0.4 0.5 LSB 0.2 LSB fIN = 10 MHz AIN = −0.5 dBFS 1.5 0.0 −0.2 0.0 −0.5 −0.4 −1.0 −0.6 −1.5 −0.8 −1.0 −2.
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Production Data ADS5541 www.ti.com SBAS307C – MAY 2004 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) AC PERFORMANCE vs DIGITAL SUPPLY VOLTAGE AC PERFORMANCE vs DIGITAL SUPPLY VOLTAGE 90 80 SFDR (dBc) fIN = 70 MHz 88 86 84 SFDR 82 76 72 78 68 SNR 74 72 70 3.0 3.1 3.2 3.3 3.4 3.5 SFDR 74 70 76 fIN = 150MHz 78 80 SNR (dBFS) SNR (dBFS) SFDR (dBc) At TA = +25°C, AVDD = DRVDD = 3.
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Production Data ADS5541 www.ti.
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Production Data ADS5541 www.ti.com SBAS307C – MAY 2004 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = DRVDD = 3.3V, sampling rate = 105MSPS, 50% clock duty cycle, DLL On, 3VPP differential clock, and –1dBFS differential input, unless otherwise noted.
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Production Data ADS5541 www.ti.com SBAS307C – MAY 2004 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = DRVDD = 3.3V, sampling rate = 105MSPS, 50% clock duty cycle, DLL On, 3VPP differential clock, and –1dBFS differential input, unless otherwise noted.
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Production Data ADS5541 www.ti.com SBAS307C – MAY 2004 – REVISED FEBRUARY 2007 APPLICATION INFORMATION THEORY OF OPERATION The ADS5541 is a low-power, 14-bit, 105MSPS, CMOS, switched capacitor, pipeline ADC that operates from a single 3.3V supply. The conversion process is initiated by a falling edge of the external input clock.
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Production Data ADS5541 www.ti.com SBAS307C – MAY 2004 – REVISED FEBRUARY 2007 This differential input topology produces a high level of ac performance for high sampling rates. It also results in a very high usable input bandwidth, especially important for high intermediate-frequency (IF) or undersampling applications. The ADS5541 requires each of the analog inputs (INP, INM) to be externally biased around the common-mode level of the internal circuitry (CM, pin 17).
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Production Data ADS5541 www.ti.com SBAS307C – MAY 2004 – REVISED FEBRUARY 2007 When it is necessary to buffer or apply a gain to the incoming analog signal, it is possible to combine single-ended operational amplifiers with an RF transformer, or to use a differential input/output amplifier without a transformer, to drive the input of the ADS5541.
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Production Data ADS5541 www.ti.com SBAS307C – MAY 2004 – REVISED FEBRUARY 2007 RS RG RF +5V RT +3.3V 10µF 0.1µF RIN VOCM 1µF THS4503 10µF RG INP ADS5541 14-Bit / 105MSPS INM CM RIN −5V 0.1µF 10 Ω RF 0.1µF Figure 42. Using the THS4503 with the ADS5520 POWER-SUPPLY SEQUENCE The preferred mode of power-supply sequencing is to power up AVDD first, followed by DRVDD. Raising both supplies simultaneously is also a valid power-supply sequence.
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Production Data ADS5541 www.ti.com SBAS307C – MAY 2004 – REVISED FEBRUARY 2007 CLOCK INPUT The ADS5541 clock input can be driven with either a differential clock signal or a single-ended clock input, with little or no difference in performance between both configurations. The common-mode voltage of the clock inputs is set internally to CM (pin 17) using internal 5kΩ resistors that connect CLKP (pin 10) and CLKM (pin 11) to CM (pin 17), as shown in Figure 45.
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Production Data ADS5541 www.ti.com SBAS307C – MAY 2004 – REVISED FEBRUARY 2007 Bandpass filtering of the source can help produce a 50% duty cycle clock and reduce the effect of jitter. When using a sinusoidal clock, the clock jitter further improves as the amplitude is increased. In that sense, using a differential clock allows for the use of larger amplitudes without exceeding the supply rails and absolute maximum ratings of the ADC clock input.
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Production Data ADS5541 www.ti.com SBAS307C – MAY 2004 – REVISED FEBRUARY 2007 The timing characteristics of the digital outputs change for sampling rates below the 105MSPS maximum sampling frequency. Table 5 and Table 6 show the setup, hold, and input clocks to output data delays, and rise and fall times for different sampling frequencies with the DLL on and off, respectively.
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ADS5541 Production Data www.ti.com SBAS307C – MAY 2004 – REVISED FEBRUARY 2007 SERIAL PROGRAMMING INTERFACE The ADS5541 has internal registers for the programming of some of the modes described in the previous sections. The registers should be reset after power-up by applying a 2µs (minimum) high pulse on RESET (pin 35); this pulse also resets the entire ADC and sets the data outputs to low. This pin has a 200kΩ internal pullup resistor to AVDD. The programming is done through a three-wire interface.
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Production Data ADS5541 www.ti.com SBAS307C – MAY 2004 – REVISED FEBRUARY 2007 Changes from B Revision (March 2006) to C Revision ................................................................................................. Page • Added MIN and MAX values for offset error and gain error, footnote for gain error. ...........................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS5541IPAPR Package Package Pins Type Drawing HTQFP PAP 64 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 13.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.0 1.5 16.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS5541IPAPR HTQFP PAP 64 1000 367.0 367.0 45.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.