Datasheet
4.4 Test Result With Onboard VCXO and Differential LVPECL Clock
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
dBFs
0 10M 20M 30M 40M 50M 60M 70M 80M 90M 100M 110M 122.86
f-Frequency-Hz
SNR=70.35dBFs,
SINAD=70.29dBFs,
SFDR=90.39dBc,
THD=88.89DBFs,
ENOB=11.38bits
5 Physical Description
5.1 PCB Layout
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Physical Description
For the same setup as explained in the previous section, when Clock Option 3 (Table 5 ) was used, the
FFT was captured as shown in Figure 9 . The test results with Clock Option 2 are better than with Clock
Option 3. That is why Option 2 (clock with crystal filter) is recommended over the differential LVPECL
output.
Figure 9. ADC Performance With Clock Through Onboard VCXO,
CDCE72010 Configured for Differential LVPECL Output
This section describes the physical characteristics and printed-circuit board (PCB) layout of the EVM.
The EVM is constructed on a six-layer, 0.062-inch-thick, PCB using FR-4 material. The individual layers
are shown in Figure 10 through Figure 15 . The layout features a common ground plane; however, similar
performance can be obtained with careful layout using a split ground plane.
SLWU061A – December 2008 – Revised June 2009 ADS61x9/55xxEVM 21
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