Datasheet

TI ADC SPI Control Interface www.ti.com
Table 8. ADS6149 Frequently Used Registers
Default Value Alternate Value
ADS6149 Reset
2s Complement/offset Binary controlled by the DFS pin Straight Binary or 2s complement
CMOS/LVDS controlled by the DFS pin DDR LVDS or CMOS
Power Down: OFF Power Down On
No Fine Gain 0 to 6 dB of gain in 0.5-dB increments
INT Reference controlled by the MODE pin EXT Reference or internal reference
High-speed operation (>100 MHz sampling) Low-Speed operation
Test Mode: None Multiple Options Test
The SPI control of the ADC register space may at a future date also be controlled by the FPGA that is on
the TSW1200 Capture Card. The SPI signals SCLK, SEN, and SDATA can be configured to be driven by
a board plugged into the connector J10. By default, three 0- Ω resistors are installed to connect these three
SPI signals to the USB port that is controlled by the SPI software. These three 0- Ω resistors can be
moved to allow the SPI port to be controlled by J10 instead.
ADS61x9/55xxEVM 18 SLWU061A – December 2008 – Revised June 2009
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