Datasheet

2.2.4 Digital Outputs
www.ti.com Circuit Description
depends on the end application. The TI schematic provides an example of a filter that is designed for the
frequency band of 10 MHz to 58 MHz. When using the suggested filter, be sure to consider the proper
value for R23 and R24 resistors, as the ADC may impose limits on how large these resistors may be while
the amplifier may impose limits on how low an impedance it can drive. A key point when designing a filter
is to design it for proper load termination. Care must be taken when supplying the input to the board, and
ensure that the source impedance is 50 Ω . Results can vary due to mismatching of the various source and
termination impedances.
The LVDS digital outputs can be accessed through the J10 output connector. A parallel 100- Ω termination
resistor must be placed at the receiver to properly terminate each LVDS data pair. These resistors are
required if the user wants to analyze the signals on an oscilloscope or a logic analyzer. The ADC
performance also can be quickly evaluated using the TSW1200 boards as explained in the next section.
The TSW1200 automatically terminates the LVDS outputs once the TSW1200 is connected to J10.
Alternatively, the ADS61x9/55xx is supplied with a breakout-board to easily connect the LVDS outputs to a
logic analyzer pod. This LVDS breakout-board also properly terminates the LVDS outputs once the
breakout board is connected to J10.
The ADS6149 and most other ADCs that may be evaluated on this EVM also have an option to output the
digitized parallel data in the form of single-ended CMOS. If single-ended CMOS is desired, header post
connector J5 is provided for the CMOS output. In order to use the header J5, a CMOS buffer U7 must be
installed in place of a bank of 0-ohm resistors that by default steer the outputs to the LVDS connector J10.
SLWU061A – December 2008 – Revised June 2009 ADS61x9/55xxEVM 15
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