Datasheet

2.2.2.1 Clock Option 1
2.2.2.2 Clock Option 2
Circuit Description www.ti.com
Table 4. Clock Input Jumper Description
EVM Banana Description Jumper Setting
Jack
J18 ENABLE VCXO1 TC0-2111 1-2 → VCXO enabled 2-3 → VCXO Disabled
J19 Clock supply
J14 CDCE72010 power down 1-2 → CDCE72010 is power down; Open → CDCE72010 is on
J15 CDCE72010 Reset 1-2 → Reset , Open → Normal operation. (Default)
SJP4 Clock In or CDC Ref. Jumper 1-2 → J19 supplies clock directly to ADC; 2-3 → Reference clock for
CDCE72010
SJP7 Clock input to +ve terminal of T4 1-2 → Connects J19 to ADC; 3-4 → Connects Y0 output of CDCE72010
for ADC clock (This path has crystal filter) to ADC; 5-6 → Connects Y1P (Differential
LVPECL clock output of CDCE72010) to ADC
SJP6 Clock input to -ve terminal of T4 for 1-2 → Connects to ground (Default); 2-3 → Connects to Y1N (Differential
ADC clock clock output of CDCE72010) only to be used with Y1P.
JP8 Mode select pin for CDCE72010 1-2 → High (default), see data sheet of CDCE72010; 2-3 → Ground
SJP8 PLLOCK LED 1-2 → Connects to D3 diode; 2-3 → Ground through 10-nF capacitor
JP10 Aux_sel pin for CDCE72010 1-2 → High, see data sheet of CDCE72010; 2-3 → Ground (Default)
Table 5. EVM Clock Input Options
EVM Evaluation Jumper Changes Required Frequency CDC Configuration Comments
Option Goal Input on J19 Description
1 Evaluate ADC J18 → 2-3; SJP4 → 1-2; SJP7 → ADC's NA Default
performance 1-2; SJP6 → 1-2; J14 → 1-2; J15 → Sampling
using a No shunt; Frequency
sinusoid clock.
2 Evaluate ADC J18 → 1-2; SJP4 → 2-3; SJP7 → 20M for Divide VCXO Maximum
performance 3-4; SJP6 → 1-2; J14 → No shunt; VCXO@983.0 frequency by 4, output performance.
using a crystal J15 → No shunt; 4 MHz on Y0
filtered
LVCMOS clock
derived from
CDCE72010
3 Evaluate ADC J18 → 1-2; SJP4 → 2-3; SJP7 → 20M for Divide VCXO Not recommended for
performance 5-6; SJP6 → 2-3; J14 → No shunt; VCXO@983.0 frequency by 4, most applications
using a J15 → No shunt; 4 MHz differential LVPECL
differential Clock output on Y1P
LVPECL clock and Y1N
The Clock Option 1 provides a clock to ADC directly from an external source. For the direct supply of the
clock to the ADC, a single-ended square or sinusoidal clock input must be applied to J19. The clock
frequency must be within the maximum frequency specified for the ADC. The clock input is converted to a
differential signal by a Mini-Circuits™ ADT4-1WT, which has an impedance ratio of 4, implying that
voltage applied on J19 is stepped up by a factor of 2. ADC performance in this case depends on the clock
source quality. This option is also the default configuration on the EVM, when it is shipped from the
factory. The test result using this option is shown in Figure 7 .
Option 2 uses the onboard VCXO and CDCE72010 to provide a clock to the ADC. The CDCE72010 is
used in SPI mode which uses the internal EEPROM to configure the CDCE72010. The EEPROM is
programmed in the factory for a divide-by-4 configuration. The EEPROM configuration is shown in
Figure 4 . The clock at J19 is the reference clock for CDCE72010. The VCXO frequency can be calculated
as Fvcxo = Fout x 4 (Fout is the frequency output U0 and U1). The reference clock for CDCE72010 is
calculated from Ref Clock = (Fvcxo x 125)/(48 x 128). This is the clock-to-M divider. When VCXO of
frequency 983.04 MHz is used, the calculation results in a reference clock of 20 MHz; the clock output on
12 ADS61x9/55xxEVM SLWU061A – December 2008 – Revised June 2009
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