Datasheet

2.2.2 Clock Input
www.ti.com Circuit Description
The clock can be supplied to the ADC in one of several ways. The default clocking option is to supply a
single-ended clock directly to the SMA connecter J19 directly, and this clock is converted to differential
and AC coupled to the ADC by transformer coupling. The clock input must be from a clean, low-jitter
source and is commonly filtered by a narrow bandpass filter. The clock amplitude is commonly set to
about 1.5-V peak-to-peak, and the amplitude offset is not an issue due to the AC coupling of the clock
input. The clock source is commonly synchronized with the clock source of the input frequency to keep the
clock and IF coherent for meaningful FFT analysis.
Alternatively, the clock may be supplied by an onboard VCXO and CDCE72010 clock buffer. The
CDCE72010 Clock Buffer has been factory programmed to output a clock to the ADC that is 1/4 the rate
of the onboard VCXO. While using this clock option, a separate 20-MHz reference clock must be supplied
to the CDCE72010 by way of the Clock Input SMA connector J19. From the CDCE7201 two clocking
options to the ADC are possible. A differential LVPECL clock output may be connected to the ADC clock
input or a single-ended CMOS clock from the CDCE72010 may be routed to the ADC transformer-coupled
clock input through an onboard crystal filter. For better performance, selecting the CMOS clock through a
crystal output is recommended. Prior to making any jumper settings, see the schematic located at the end
of this document. Table 5 displays the various clock option settings. The VCXO and crystal filter do not
come populated on the EVM by default, although the CDCE72010 Clock buffer is installed.
SLWU061A – December 2008 – Revised June 2009 ADS61x9/55xxEVM 11
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