ADS61x9/55xxEVM User's Guide Literature Number: SLWU061A December 2008 – Revised June 2009
SLWU061A – December 2008 – Revised June 2009 Submit Documentation Feedback
Contents 1 2 3 4 Overview ............................................................................................................................. 5 1.1 Purpose..................................................................................................................... 5 1.2 EVM Quick-Start Procedure ............................................................................................. 5 Circuit Description .........................................................................
www.ti.com List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ADS61x9/55xx Jumpers .................................................................................................... 7 ADS61x9/55xx Surface Jumpers .......................................................................................... 8 ADS61x9/55xx Power Distribution ......................................................................................... 9 CDCE72010 EEPROM Configuration Block Diagram ..........................
User's Guide SLWU061A – December 2008 – Revised June 2009 ADS61x9/55xxEVM 1 Overview This evaluation module (EVM) user's guide gives an overview of the EVM and provides a general description of the features and functions to be considered while using this module. This EVM user's guide applies to multiple EVMs: • ADS61x9 family: – ADS6128, ADS6148, ADS6129, ADS6149, ADS61B29, ADS61B49 • ADS556x family: – ADS5560, AD5562 • ADS55xx family: – ADS5517, ADS5525, ADS5527, ADS5545, ADS5546, ADS5547. 1.
Overview www.ti.com Table 1. Jumper List Jumper Function Default Jumper Setting Interface Circuit Operational Amplifier THS4509 (Bypassed) SJP1 AMP_OUT+ 1-2 SJP2 AMP_OUT– 1-2 JP7 PD 1-2 SJP5 AMPIN- 1-2 ADC Circuit JP12 Parallel 1-2 JP11 SDA open JP9 SEN 1-2 JP15 OE open J2 DFS open J3 MODE 1-2 J1 SEN open SJP4 CLOCKIN 1-2 SJP7 CLOCKIN, Y0, Y1P SELECT 1-2 SJP6 Y1N SELECT 1-2 J14 PWRDWN CDC 1-2 Clock Interface Circuit Power Supply JP13 3.
Circuit Description www.ti.com 2 Circuit Description 2.1 Schematic Diagram The schematic diagram for this EVM is attached at the end of this document. See the schematic or relevant section of this user's guide before changing any jumpers. 2.2 Circuit Function Selection of various modes of operation of the ADS61x9/55xx is most often controlled by jumpers on the EVM, either by placing shunts on 0.025-inch square jumper posts or by installation of surface mount 0-Ω resistors.
Circuit Description www.ti.com J7 R12 (bottom) J11 5V J9 VSS- J12 VSS+ GND J5 J8 0 R102 1 J10 0 SJP2 SJP3 IN- 1 R84 SJP1 0 SJP5 R24 1 LVDS 0 IN+ 1 LVDS 0 1 R23 ADS 6149 1 J6 0 SJP7 SJP6 SJP4 J21 VCXO OUT R65 R7 (bottom) R67 USB 1 R19 (bottom) J17 R20(bottom) R66 0 1 0 SJP8 CDC OUT CLKIN J19 J20 Figure 2. ADS61x9/55xx Surface Jumpers The following sections describe the function of individual circuits.
Circuit Description www.ti.com TPS5420D Switching Regulator to 5.3 V 1 5 to 36 V TPS79501 LDO Regulator to 5 V JP19 JP17 open JP16 J7 5V Analog VDD To ADC 1 J12 TPS79633 LDO 3.3 V TPS79601 LDO 1.8 V (option for 3.3 V) Digital VDD To ADC J9 VSS + GND TPS79601 LDO 3.3 V THS4509 J11 TPS79633 LDO 3.3 V To Clock Gen. option, to USB port VSS - To Clock Generator Option To Clock Generator Option, USB Port, CMOS buffer To USB Port Figure 3.
Circuit Description www.ti.com Table 3. EVM Power Supply Options 2.2.1.1 EVM Option Evaluation Goal Jumper Changes Required Voltage on J7 Comments 1 Evaluate ADC performance using a cascaded switching power supply (TPS5420D) and LDO solution (TPS79501DCQ) JP13 → 1-2; JP14 → 1-2; JP16 → 1-2; JP19 → 2-3; JP17 → 1-2; 6 V - 36 V Maximum performance and efficiency. 2 Evaluate ADC performance using a LDO-based solution. JP13 → 1-2; JP14 → 1-2; JP16 → 1-2; JP19 → 1-2, JP17 → No shunt; 5.1 V - 5.
www.ti.com 2.2.2 Circuit Description Clock Input The clock can be supplied to the ADC in one of several ways. The default clocking option is to supply a single-ended clock directly to the SMA connecter J19 directly, and this clock is converted to differential and AC coupled to the ADC by transformer coupling. The clock input must be from a clean, low-jitter source and is commonly filtered by a narrow bandpass filter. The clock amplitude is commonly set to about 1.
Circuit Description www.ti.com Table 4. Clock Input Jumper Description EVM Banana Jack Description Jumper Setting 1-2 → VCXO enabled 2-3 → VCXO Disabled J18 ENABLE VCXO1 TC0-2111 J19 Clock supply J14 CDCE72010 power down 1-2 → CDCE72010 is power down; Open → CDCE72010 is on J15 CDCE72010 Reset 1-2 → Reset , Open → Normal operation. (Default) SJP4 Clock In or CDC Ref.
Circuit Description www.ti.com Y0 pin of CDCE72010 is 245.76 MHz. This clock is filtered using the crystal filter with center frequency of 245.76 MHz. By default, the VCXO and the crystal filter are not populated on the EVM, so that the user can populate the components depending on the end application and sampling rate. This configuration is recommended for applications requiring an onboard clock generation scheme. The test result using this option is shown in Figure 8.
Circuit Description www.ti.com Table 6. Analog Input Jumper description EVM Banana Jack Description Jumper Setting J6 Analog input single-ended. J8 Analog input, can be used with J6 for differential input Not populated J9 Power supply + Apply 5 V J11 Power Supply - Ground.
www.ti.com Circuit Description depends on the end application. The TI schematic provides an example of a filter that is designed for the frequency band of 10 MHz to 58 MHz. When using the suggested filter, be sure to consider the proper value for R23 and R24 resistors, as the ADC may impose limits on how large these resistors may be while the amplifier may impose limits on how low an impedance it can drive. A key point when designing a filter is to design it for proper load termination.
TI ADC SPI Control Interface 3 www.ti.com TI ADC SPI Control Interface This section describes the software features accompanying the EVM kit. The TI ADC SPI control software provides full control of the SPI interface, allowing users to write to any of the ADC registers found in the ADC data sheet. For most ADS6149 (and other ADCs evaluated on this EVM) performance evaluations, users do not need to use the TI SPI control software to get evaluation results.
TI ADC SPI Control Interface www.ti.com 3.2 Setting Up the EVM for ADC SPI Control Users who want to use the ADC SPI interface must configure four jumpers for proper control of the SPI bus. By default, the EVM comes with the ADC configured in parallel mode. In order to use the SPI interface to control the ADC modes of operation, users must: • Move jumper JP12 to short positions 2–3, which places the ADC in serial operation mode.
TI ADC SPI Control Interface www.ti.com Table 8. ADS6149 Frequently Used Registers Default Value Alternate Value ADS6149 Reset 2s Complement/offset Binary controlled by the DFS pin Straight Binary or 2s complement CMOS/LVDS controlled by the DFS pin DDR LVDS or CMOS Power Down: OFF Power Down On No Fine Gain 0 to 6 dB of gain in 0.
Evaluation www.ti.com 4 Evaluation 4.1 TSW1200 Capture Board The TSW1200 board can be used to analyze the performance of the EVM. The TSW1200EVM is a circuit board that assists designers in prototyping and evaluating the performance of high-speed ADCs that feature parallel or serialized LVDS outputs. The TSW1200 has the LVDS 100-Ω termination resistor on the input interface for ADC outputs. To start the TSW1200 software, note the following points. 1 7 2 6 3 4 5 Figure 6.
Evaluation www.ti.com 0 SNR = 71.91 dBFs, SINAD = 71.78 dBFs, SFDR = 87.96 dBc, THD = 87.07 DBFs, ENOB = 11.63 bits -10 -20 -30 -40 dBFs -50 -60 -70 -80 -90 -100 -110 -120 0 10M 20M 30M 40M 50M 60M 70M f - Frequency - Hz 80M 90M 100M 110M 124.5 Figure 7. Quick-Setup Test Result. 4.3 Test Result With Onboard VCXO and Clock Through Crystal Filter This test uses the VCXO of frequency 983.04 MHz.
Physical Description www.ti.com 4.4 Test Result With Onboard VCXO and Differential LVPECL Clock For the same setup as explained in the previous section, when Clock Option 3 (Table 5) was used, the FFT was captured as shown in Figure 9. The test results with Clock Option 2 are better than with Clock Option 3. That is why Option 2 (clock with crystal filter) is recommended over the differential LVPECL output. 0 SNR = 70.35 dBFs, SINAD = 70.29 dBFs, SFDR = 90.39 dBc, THD = 88.89 DBFs, ENOB = 11.
Physical Description www.ti.com Figure 10.
Physical Description www.ti.com Figure 11.
Physical Description www.ti.com Figure 12.
Physical Description www.ti.com Figure 13.
Physical Description www.ti.com Figure 14.
Physical Description www.ti.com Figure 15.
Physical Description www.ti.com Figure 16.
Physical Description www.ti.com Figure 17.
Physical Description 5.2 Bill of Materials Qty Reference 16 30 www.ti.com Not Installed Value Foot Print Part Number Manufacturer Toleran ce Volt C11, C12, C32, C85, C87–C89, C92, C96–C103 10 nF 603 GCM188R71H103KA37D Panasonic 10% 50V 17 C13, C47, C50, C53, C56,C61, C62, C70, C72,C78–C81, C83, C135, C145, C146 0.1 µF 603 ECJ-1VB1C104K Panasonic 10% 16V 5 C15, C33, C34, C68, C69 0.1 µF 603 GRM188R71H104KA93D Murata 5% 50V 1 C41 2.
Physical Description www.ti.com Qty Reference Not Installed Value Foot Print Part Number Manufacturer Toleran ce Volt Watt 1 D2 B340A-13-F DIODE_SM_DO_214AC B340A-13-F Diodes Inc 1 D3 BLUE DIFUSED DIODE_SM_HSMN_C170 HSMN-C170 AVAGO 0 FLT1 245.
Physical Description Qty 32 Reference Not Installed www.ti.com Value Foot Print Part Number Manufacturer Toleran ce Volt Watt 1 R49 10K 603 ERJ-3GEYJ103V Panasonic 5% 1/10W 1 R50 2.21K 603 ERJ-3EKF2211V Panasonic 1% 1/10W 1 R51 4.7K 603 ERJ-3EKF4R71V Panasonic 1% 1/10W 0 R52 10K 603 ERJ-3EKF1002V Panasonic 1% 1/10W 1 R53 1.5K 603 ERJ-3EKF1501V Panasonic 5% 1/10W 0 R54, R65–R67 0Ω 603 ERJ-3GEY0R00V Panasonic 5% 1/10W 2 R55, R56 26.
www.ti.com 5.3 Physical Description Schematic Drawings The schematic drawings appear on the following page.
5 4 3 2 (SHORT 1-2) AMP- 2 END 4 3 2 5 3 SJP3 1 3 IN- 4 3 2 5 AMP_IN- 2 END DNI SJP1 R82 1 2 1 ZERO DNI (NO SHUNT) AMP+ (SHORT 1-2) 1 2 3 WBC1-1 1 5 2 4 3 DNI R25 49.9 DNI T1 WBC1-1 3 R22 49.9 R84 ZERO 5 IN_P 1 6 T2 C33 .1uF C106 150pF DNI R24 24.9 4.99 C74 3.3pF DNI VCM SH3 C68 1 C34 .1uF 2 .1uF C95 5.6pF DNI R81 49.9 DNI C105 150pF DNI R23 24.9 C15 1 R68 49.9 DNI 2 SH3 R100 49.9 D C148 3.3pF R26 R101 49.9 IN_M SH3 4.99 .
5 4 3 1 1. OPTION 1 (DEFAULT): SJP4 - SHORT 1 & 2; SJP7 - SHORT 1 & 2; SJP6 - SHORT 1 &2. TP8 TP7 2 2. OPTION 2 (CDC SINGLE-ENDED CLOCK INPUT): SJP4 - SHORT 2 & 3; SJP7 - SHORT 3 & 4; SJP6 - SHORT 1 & 2. 3. OPTION 3 (CDC DIFERENTIAL CLOCK INPUT): SJP4 - SHORT 2 & 3; SJP7 - SHORT 5 & 6; SJP6 - SHORT 2 & 3. 2 C62 .1uF 6 5 4 CLOCKIN END C63 22uF (SHORT 1-2) R31 121 1/10W 1% DNI T4 CLKIN 1 6 2 5 3 4 1 2 C127 2 1 .022uF C128 2 1 100pF DNI 1 3.3V_AUX L17 C115 1 2 .
5 4 3 2 1 U1 is compatible with: ADC +3.3VA D6_D7-P D6_D7-M D4_D5-P D4_D5-M D2_D3-P D2_D3-M 1 SH5 SH5 SH5 SH5 SH5 SH5 SH5 SH5 SH5 SH5 SH5 SH5 PARALLEL INTERFACE R6 10K JP12 +3.3VA 1 3 (SHORT 1-2) SH5 OVR SH5 CLKOUT_M SH5 CLKOUT_P TP10 DFS 2 SH2 CLK+ SH2 CLK- JP15 DRGND DRVDD OVR CLKOUTM CLKOUTP DFS OE AVDD AGND CLKP CLKM AGND U1 ADS61X9 11 RESET 2 SERIAL INTERFACE 1 SEN 2 100 R20 SCLK +3.
5 4 3 2 1 D D 5V_AUX 93C66B 1 C88 10nF 2 1 2 1 C87 10nF C89 10nF 2 2 C86 10uF 2 + C91 27pF 2 2 10nF C R49 10K U5 6.0000MHz 2 1 5V_AUX C92 1 C90 27pF 1 5V_AUX 1 1 Y1 8 7 6 5 VCC ORG NC VSS 1 2 3 4 CS CLK DI DOUT C 1 5V_AUX R50 2.21K SCLK 2 1 32 31 30 29 28 27 26 25 SDATA 2 1K @ 100MHZ 1 4 C93 .01uF 2 3 1 2 R53 1.5K R55 26.
5 4 3 SH3 SH3 SH3 SH3 C103 10nF 8 7 6 5 RN4 0 ohm 0 ohm SH3 SH3 SH3 SH3 D6_D7-P D6_D7-M D4_D5-P D4_D5-M RN5 1 2 3 4 SH3 SH3 SH3 SH3 D2_D3-P D2_D3-M D0_D1-P D0_D1-M 1 2 3 4 D8_D9_P D8_D9_M CLKOUTP CLKOUTM 8 7 6 5 D6_D7_P D6_D7_M D4_D5_P D4_D5_M 8 7 6 5 D2_D3_P D2_D3_M D0_D1_P D0_D1_M RN6 0 ohm R70 0 OHM CONN_QTH_30X2-D-A 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 SH3 OVR D12_D13_P D12_D13_M D10_D11_P D10_D11_M D8_D9_P D8_D9_M D6_D7_P D6_D7_
5 4 3 2 1 5V_AUX VIN ENA NC1 NC2 GND BOOT 1 2 R94 1 8 VSNS 4 5.3V 1 1 2 MSS1038-683ML 0 ohm PH R95 2.2 D2 B340A-13-F C189 470pF TPS5420D C146 .1uF 16V +C67 47uF 20V PWR_IN U12 2 1 2 3 3 (SHUNT 1-2) R98 10K C186 1uF 20% 25V EN OUT IN NR/FB GND GND (SHUNT 1-2) 3 2 PWR_IN 1 5V 4 5 6 C187 C414 1uF 15pF 20% 25V R99 93.1K TPS79501 1 D 7 5 2 3 6 C145 .1uF 16V C188 4.7uF 20% 50V JP16 5.3V 2 2 1 1 (NO SHUNT) RED L22 68uH C142 0.
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