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RESET TIMING CHARACTERISTICS
SERIAL PROGRAMMING INTERFACE CHARACTERISTICS
ADS5500
SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007
TIMING CHARACTERISTICS (continued)
Typ values given at T
A
= 25 ° C, min and max specified over the full recommended operating temperature range, sampling
rate = 125 Msps, 50% clock duty cycle, AV
DD
= DRV
DD
= 3.3 V, 3-V
PP
differential clock, and C
LOAD
= 10 pF, (unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Time to valid data after coming out of software power 1000
Clock
down
Wake-up time
Cycles
Time to valid data after stopping and restarting the clock 1000
Latency Time for a sample to 17.5 Clock
propagate to the ADC outputs 17.5 Cycles
Clock Cycles
Typ values given at T
A
= 25 ° C, min and max specified over the full recommended operating temperature range, AV
DD
=
DRV
DD
= 3.3 V, 3-V
PP
differential clock(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SWITCHING SPECIFICATION
t
1
Power-on delay Delay from power on of AV
DD
and DRV
DD
to RESET pulse 10 ms
t
2
Reset pulse width Pulse width of active RESET signal 2 µ s
t
3
Register write delay Delay from RESET disable to SEN active 2 µ s
Power-up time Delay from power-up of AV
DD
and DRV
DD
to output stable 40 ms
Figure 2. Reset Timing Diagram
The device has a three-wire serial interface. The device latches the serial data SDATA on the falling edge of
serial clock SCLK when SEN is active.
• Serial shift of bits is enabled when SEN is low. SCLK shifts serial data at falling edge.
• Minimum width of data stream for a valid loading is 16 clocks.
• Data is loaded at every 16th SCLK falling edge while SEN is low.
• In case the word length exceeds a multiple of 16 bits, the excess bits are ignored.
• Data can be loaded in multiple of 16-bit words within a single active SEN pulse.
• The first 4-bit nibble is the address of the register while the last 12 bits are the register contents.
7
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