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TIMING CHARACTERISTICS
TIMING CHARACTERISTICS
(1) (2)
ADS5500
SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007
NOTE: It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above
timing matches closely with the specified values.
Figure 1. Timing Diagram
Typ values given at T
A
= 25 ° C, min and max specified over the full recommended operating temperature range, sampling
rate = 125 Msps, 50% clock duty cycle, AV
DD
= DRV
DD
= 3.3 V, 3-V
PP
differential clock, and C
LOAD
= 10 pF, (unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SWITCHING SPECIFICATION
t
A
Aperture delay Input CLK falling edge to data sampling point 1 ns
Aperture jitter (uncertainty) Uncertainty in sampling instant 300 fs
t
su
Data setup time Data valid
(3)
to 50% of CLKOUT rising edge 2.1 2.5 ns
t
h
Data hold time 50% of CLKOUT rising edge to data becoming invalid
(3)
1.7 2.1 ns
t
START
Input clock to output data valid Input clock rising edge to Data valid start delay 2.2 2.9 ns
start
(4) (5)
t
END
Input clock to output data valid Input clock rising edge to Data valid end delay 5.8 6.9 ns
end
(4)(5)
t
JIT
Output clock jitter Uncertainty in CLKOUT rising edge, peak-to-peak 150 210 ps
t
r
Output clock rise time Rise time of CLKOUT measured from 20% to 80% of 1.7 1.9 ns
DRVDD
t
f
Output clock fall time Fall time of CLKOUT measured from 80% to 20% of 1.5 1.7 ns
DRVDD
t
PDI
Input clock to output clock delay Input clock rising edge, zero crossing, to output clock 4.2 4.8 5.5 ns
rising edge 50%
t
r
Data rise time Data rise time measured from 20% to 80% of DRVDD 3.6 4.6 ns
t
f
Data fall time Data fall time measured from 80% to 20% of DRVDD 2.8 3.7 ns
Output enable (OE) to data output Time required for outputs to have stable timings w.r.t 1000 Clock
delay input clock( after OE is activated Cycles
(1) Timing parameters are ensured by design and characterization and not tested in production.
(2) See Table 5 through Table 8 in the Application Information section for timing information at additional sampling frequencies.
(3) Data valid refers to 2 V for LOGIC high and 0.8 V for LOGIC low.
(4) See the Output Information section for details on using the input clock for data capture.
(5) These specifications apply when the CLKOUT polarity is set to rising edge (according to Table 3 ). Add ½ clock period for the valid
number for a falling edge CLKOUT polarity.
6
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