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REFERENCE CIRCUIT
CLOCK INPUT
ADS5500
SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007
Using the serial interface PDN bit to power down the
device places the outputs in a high-impedance state
and only the internal reference remains on to reduce
the power-up time. The power-down mode reduces
power dissipation to approximately 180 mW.
The ADS5500 has built-in internal reference
generation, requiring no external circuitry on the
printed circuit board (PCB). For optimum
performance, it is best to connect both REFP and
REFM to ground with a 1- µ F decoupling capacitor
(the 1- Ω series resistor shown in Figure 45 is
optional). In addition, an external 56.2-k Ω resistor
should be connected from IREF (pin 31) to AGND to
set the proper current for the operation of the ADC,
as shown in Figure 45 . No capacitor should be
Figure 46. Clock Inputs
connected between pin 31 and ground; only the
56.2-k Ω resistor should be used.
When driven with a single-ended CMOS clock input,
it is best to connect CLKM (pin 11) to ground with a
0.01- µ F capacitor, while CLKP is ac-coupled with a
0.01- µ F capacitor to the clock source, as shown in
Figure 47 .
Figure 45. REFP, REFM, and IREF Connections
Figure 47. AC-Coupled, Single-Ended Clock Input
for Optimum Performance
The ADS5500 clock input can also be driven
differentially, reducing susceptibility to
common-mode noise. In this case, it is best to
The ADS5500 clock input can be driven with either a
connect both clock inputs to the differential input
differential clock signal or a single-ended clock input,
clock signal with 0.01- µ F capacitors, as shown in
with little or no difference in performance between
Figure 48 .
both configurations. The common-mode voltage of
the clock inputs is set internally to CM (pin 17) using
internal 5-k Ω resistors that connect CLKP (pin 10)
and CLKM (pin 11) to CM (pin 17), as shown in
Figure 46 .
Figure 48. AC-Coupled, Differential Clock Input
For high input frequency sampling, it is
recommended to use a clock source with very low
jitter. Additionally, the internal ADC core uses both
edges of the clock for the conversion process. This
means that, ideally, a 50% duty cycle should be
provided. Figure 49 shows the performance variation
of the ADC versus clock duty cycle.
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