Datasheet

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DEFINITION OF SPECIFICATIONS
ADS5500
SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007
PIN CONFIGURATION (continued)
PIN ASSIGNMENTS (continued)
TERMINAL
NO. OF
I/O DESCRIPTION
PINS
NAME NO.
DR
GND
1, 42, 48, 50, 57, 59 6 I Output driver ground
INP 19 1 I Differential analog input (positive)
INM 20 1 I Differential analog input (negative)
REFP 29 1 O Reference voltage (positive); 1- µ F capacitor to GND
REFM 30 1 O Reference voltage (negative); 1- µ F capacitor to GND
IREF 31 1 I Current set; 56.2-k Ω resistor to GND; do not connect capacitors
CM 17 1 O Common-mode output voltage
RESET 35 1 I Reset (active high), internal 200-k Ω resistor to AVDD
(1)
OE 41 1 I Output enable (active high)
DFS 40 1 I Data format and clock out polarity select
(2) (3)
CLKP 10 1 I Data converter differential input clock (positive)
CLKM 11 1 I Data converter differential input clock (negative)
SEN 4 1 I Serial interface chip select
(3)
SDATA 3 1 I Serial interface data
(3)
SCLK 2 1 I Serial interface clock
(3)
D0 (LSB)–D13(MSB) 44-47, 51-56, 60-63 14 O Parallel data output
OVR 64 1 O Over-range indicator bit
CLKOUT 43 1 O CMOS clock out in sync with data
NOTE: PowerPAD must be connected to analog ground.
(1) If unused, the RESET pin should be tied to AGND. See the serial programming interface section for details.
(2) Table 3 defines the voltage levels for each mode selectable via the DFS pin.
(3) Pins OE, DFS, SEN, SDATA, and SCLK have internal clamping diodes to the DRVDD supply. Any external circuit driving these pins
must also run off the same supply voltage as DRVDD.
Minimum Conversion Rate
Analog Bandwidth
The minimum sampling rate at which the ADC
The analog input frequency at which the power of the
functions.
fundamental is reduced by 3 dB with respect to the
low frequency value. Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions at analog
Aperture Delay
input values spaced exactly 1 LSB apart. The DNL is
The delay in time between the falling edge of the
the deviation of any single step from this ideal value,
input sampling clock and the actual time at which the
measured in units of LSBs.
sampling occurs.
Integral Nonlinearity (INL)
Aperture Uncertainty (Jitter)
The INL is the deviation of the ADC's transfer
The sample-to-sample variation in aperture delay.
function from a best fit line determined by a least
squares curve fit of that transfer function, measured
Clock Pulse Width/Duty Cycle
in units of LSBs.
The duty cycle of a clock signal is the ratio of the
time the clock signal remains at a logic high (clock
Gain Error
pulse width) to the period of the clock signal. Duty
The gain error is the deviation of the ADC's actual
cycle is typically expressed as a percentage. A
input full-scale range from its ideal value. The gain
perfect differential sine-wave clock results in a 50%
error is given as a percentage of the ideal input
duty cycle.
full-scale range. Gain error does not account for
variations in the internal reference voltages (see the
Maximum Conversion Rate
Electrical Specifications section for limits on the
The maximum sampling rate at which certified
variation of V
REFP
and V
REFM
).
operation is given. All parametric testing is performed
at this sampling rate unless otherwise noted.
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