Datasheet

ADS5402

USB

SPI Port

Trigger

Analog

Inputs

Clock

Sync

(not Installed)

Power

Supply

Circuits

LVDS DDR

CLK, DATA

J11

Introduction

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1 Introduction

1.1 EVM Block Diagram

Figure 1 shows a simplified block diagram of the default configuration of the EVM. Each analog input is

supplied to the EVM through a single-ended SMA connection, then transformer coupled to turn the single-

ended signal into a balanced differential signal, and then input to the ADS540x. A dual transformer input

circuit is used for better phase and amplitude balance of the input signal than would typically be produced

by a single transformer input circuit.

Figure 1. Simplified EVM Block Diagram

The clock input is supplied by way of a single-ended signal to an SMA connector and transformer coupled

to produce a differential clock signal for the ADS540x.

Power to the EVM is supplied using a single 5-V connection by way of banana jacks. All necessary

voltages for the ADS540x are derived from the 5-V input connection.

For the ADS54T0x EVM, a trigger signal may be input to the trigger SMA connector to trigger the burst of

high resolution sample data from the ADC. This trigger signal may be sourced by the TSW1400 Capture

Card.

ADS540x and ADS54T0x Evaluation Module (EVM) SLAU450–July 2012

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