Datasheet

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
IN8
N
IN8
P
AVSS
IN7
N
IN7
P
AVSS
IN6
N
IN6
P
AVSS
IN5
N
IN5
P
AVSS
LVSS
LVDD
OUT8
N
OUT8
P
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
IN1
P
IN1
N
AVSS
IN2
P
IN2
N
AVSS
IN3
P
IN3
N
AVSS
IN4
P
IN4
N
LVSS
PD
LVSS
OUT1
P
OUT1
N
RESET
SCLK SDATA
CS
AVDD CLK
N
CLK
P
AVDD INT/EXT REF
T
REF
B
V
CM
TP I
SET
AVDD AVDD
OUT2
P
OUT2
N
OUT3
P
OUT3
N
OUT4
P
OUT4
N
ADCLK
P
ADCLK
N
LCLK
P
LCLK
N
OUT5
P
OUT5
N
OUT6
P
OUT6
N
OUT7
P
OUT7
N
64
63 62 61 60 59 58
57 56 55 54
17 18 19 20 21 22 23 24 25 26 27
53 52 51 50 49
28 29 30 31 32
ADS528X
ADS5281
ADS5282
www.ti.com SBAS397I –DECEMBER 2006–REVISED JUNE 2012
QFN-64 PowerPAD
TOP VIEW
Table 3. PIN DESCRIPTIONS: QFN-64
PIN NAME DESCRIPTION PIN NUMBER # OF PINS
ADCLK
N
LVDS frame clock (1X)—negative output 24 1
ADCLK
P
LVDS frame clock (1X)—positive output 23 1
AVDD Analog power supply, 3.3V 49, 50, 57, 60 4
AVSS Analog ground 3, 6, 9, 37, 40, 43, 46 7
Negative differential clock input
CLK
N
59 1
Tie CLK
N
to 0V for a single-ended clock
CLK
P
Positive differential clock input 58 1
CS Serial enable chip select—active low digital input 61 1
IN1
N
Negative differential input signal, channel 1 2 1
IN1
P
Positive differential input signal, channel 1 1 1
IN2
N
Negative differential input signal, channel 2 5 1
IN2
P
Positive differential input signal, channel 2 4 1
IN3
N
Negative differential input signal, channel 3 8 1
IN3
P
Positive differential input signal, channel 3 7 1
IN4
N
Negative differential input signal, channel 4 11 1
IN4
P
Positive differential input signal, channel 4 10 1
IN5
N
Negative differential input signal, channel 5 39 1
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