Datasheet

ADS5281
ADS5282
SBAS397I –DECEMBER 2006–REVISED JUNE 2012 www.ti.com
Table 2. PIN DESCRIPTIONS: TQFP-80 (continued)
PIN NAME DESCRIPTION PIN NUMBER # OF PINS
IN2
P
Positive differential input signal, channel 2 5 1
IN3
N
Negative differential input signal, channel 3 10 1
IN3
P
Positive differential input signal, channel 3 9 1
IN4
N
Negative differential input signal, channel 4 13 1
IN4
P
Positive differential input signal, channel 4 12 1
IN5
N
Negative differential input signal, channel 5 49 1
IN5
P
Positive differential input signal, channel 5 48 1
IN6
N
Negative differential input signal, channel 6 52 1
IN6
P
Positive differential input signal, channel 6 51 1
IN7
N
Negative differential input signal, channel 7 56 1
IN7
P
Positive differential input signal, channel 7 55 1
IN8
N
Negative differential input signal, channel 8 59 1
IN8
P
Positive differential input signal, channel 8 58 1
INT/EXT Internal/external reference mode select input 69 1
I
SET
Bias pin—56.2kΩ to ground 64 1
LCLK
N
LVDS bit clock (6X)—negative output 20 1
LCLK
P
LVDS bit clock (6X)—positive output 19 1
LVDD Digital and I/O power supply, 1.8V 25, 35 2
LVSS Digital ground 15, 17, 18, 26, 36, 43, 44, 46 8
NC No connection (or connect to ground) 62 1
OUT1
N
LVDS channel 1—negative output 22 1
OUT1
P
LVDS channel 1—positive output 21 1
OUT2
N
LVDS channel 2—negative output 24 1
OUT2
P
LVDS channel 2—positive output 23 1
OUT3
N
LVDS channel 3—negative output 28 1
OUT3
P
LVDS channel 3—positive output 27 1
OUT4
N
LVDS channel 4—negative output 30 1
OUT4
P
LVDS channel 4—positive output 29 1
OUT5
N
LVDS channel 5—negative output 32 1
OUT5
P
LVDS channel 5—positive output 31 1
OUT6
N
LVDS channel 6—negative output 34 1
OUT6
P
LVDS channel 6—positive output 33 1
OUT7
N
LVDS channel 7—negative output 38 1
OUT7
P
LVDS channel 7—positive output 37 1
OUT8
N
LVDS channel 8—negative output 40 1
OUT8
P
LVDS channel 8—positive output 39 1
PD Power-down input 16 1
REF
B
Negative reference input/output 66 1
REF
T
Positive reference input/output 67 1
RESET Active low RESET input 45 1
SCLK Serial clock input 78 1
SDATA Serial data input 77 1
TP Test pin, do not use 61 1
V
CM
Common-mode output pin, 1.5V output 65 1
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