Datasheet

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
AVDD
IN8
N
IN8
P
AVSS
IN7
N
IN7
P
AVDD
AVSS
IN6
N
IN6
P
AVSS
IN5
N
IN5
P
AVDD
LVSS
RESET
LVSS
LVSS
ADCLK
N
ADCLK
P
AVSS
OUT1
P
AVSS
OUT1
N
SCLK
OUT2
P
SDATA
OUT2
N
CS
LVDD
AVDD
LVSS
AVSS
OUT3
P
AVSS
OUT3
N
CLK
N
OUT4
P
CLK
P
OUT4
N
AVDD
OUT5
P
INT/EXT
OUT5
N
AVSS
OUT6
P
REF
T
OUT6
N
REF
B
LVDD
V
CM
LVSS
I
SET
OUT7
P
AVDD
OUT7
N
NC
OUT8
P
TP
OUT8
N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
AVDD
IN1
P
IN1
N
AVSS
IN2
P
IN2
N
AVDD
AVSS
IN3
P
IN3
N
AVSS
IN4
P
IN4
N
AVDD
LVSS
PD
LVSS
LVSS
LCLK
P
LCLK
N
80 79 78 77 76 75 74 73 72 71 70
21 22 23 24 25 26 27 28 29 30 31
69
32
33 34 35 36 37 38 39 40
68 67 66 65 64 63 62 61
ADS528x
ADS5281
ADS5282
www.ti.com SBAS397I –DECEMBER 2006–REVISED JUNE 2012
PIN CONFIGURATIONS
TQFP-80
TOP VIEW
Table 2. PIN DESCRIPTIONS: TQFP-80
PIN NAME DESCRIPTION PIN NUMBER # OF PINS
ADCLK
N
LVDS frame clock (1X)—negative output 42 1
ADCLK
P
LVDS frame clock (1X)—positive output 41 1
AVDD Analog power supply, 3.3V 1, 7, 14, 47, 54, 60, 63, 70, 75 9
AVSS Analog ground 4, 8, 11, 50, 53, 57, 68, 73, 74, 79, 80 11
Negative differential clock
CLK
N
72 1
Tie CLK
N
to 0V for a single-ended clock
CLK
P
Positive differential clock 71 1
CS Serial enable chip select—active low digital input 76 1
IN1
N
Negative differential input signal, channel 1 3 1
IN1
P
Positive differential input signal, channel 1 2 1
IN2
N
Negative differential input signal, channel 2 6 1
Copyright © 2006–2012, Texas Instruments Incorporated 7