Datasheet

CLK
P
CLK
N
CMOSClockInput
0.1 Fm
0.1 Fm
CLK
P
CLK
N
CMOSSingle-Ended
Clock
0V
CLK
P
CLK
N
DifferentialSine-Wave,
PECL,orLVDSClockInput
0.1 Fm
0.1 Fm
5kW 5kW
V
CM
CLK
P
CLK
N
V
CM
ADS5281
ADS5282
www.ti.com
SBAS397I DECEMBER 2006REVISED JUNE 2012
CLOCK INPUT
The eight channels on the device operate from a
single ADCLK input. To ensure that the aperture
delay and jitter are the same for all channels, a clock
tree network is used to generate individual sampling
clocks to each channel. The clock paths for all the
channels are matched from the source point to the
sampling circuit. This architecture ensures that the
performance and timing for all channels are identical.
The use of the clock tree for matching introduces an
aperture delay that is defined as the delay between
the rising edge of ADCLK and the actual instant of
sampling. The aperture delays for all the channels
are matched to the best possible extent. A mismatch
of ±20ps (±3σ) could exist between the aperture
instants of the eight ADCs within the same chip.
Figure 39. Internal Clock Buffer
However, the aperture delays of ADCs across two
different chips can be several hundred picoseconds
apart.
The ADS528x can be made to operate either in
CMOS single-ended clock mode (default is
DIFF_CLK = 0) or differential clock mode (SINE,
LVPECL, or LVDS). When operating in the single-
ended clock mode, CLK
N
must be forced to 0V
DC
,
and the single-ended CMOS applied on the CLK
P
pin.
This operation is shown in Figure 38.
Figure 40. Differential Clock Driving Circuit
(DIFF_CLK = 1)
Figure 38. Single-Ended Clock Driving Circuit
(DIFF_CLK = 0)
When configured to operate in the differential clock
Figure 41. Single-Ended Clock Driving Circuit
mode (register bit DIFF_CLK = 1) the ADS528x clock
When DIFF_CLK = 1
inputs can be driven differentially (SINE, LVPECL, or
LVDS) with little or no difference in performance
For best performance, the clock inputs must be
between them, or with a single-ended (LVCMOS).
driven differentially in order to reduce susceptibility to
The common-mode voltage of the clock inputs is set
common-mode noise. For high input frequency
to V
CM
using internal 5k resistors, as shown in
sampling, it is recommended to use a clock source
Figure 39. This method allows using transformer-
with very low jitter. Bandpass filtering of the clock
coupled drive circuits for a sine wave clock or ac-
source can help reduce the effect of jitter. If the duty
coupling for LVPECL and LVDS clock sources, as
cycle deviates from 50% by more than 2% or 3%, it is
shown in Figure 40. When operating in the differential
recommended to enable the DCC through register bit
clock mode, the single-ended CMOS clock can be ac-
EN_DCC.
coupled to the CLK
P
input, with CLK
N
(pin 11)
connected to ground with a 0.1μF capacitor, as
shown in Figure 41.
Copyright © 2006–2012, Texas Instruments Incorporated 35