Datasheet

ADS5281
ADS5282
SBAS397I –DECEMBER 2006–REVISED JUNE 2012 www.ti.com
APPLICATION INFORMATION
The ADC output goes to a serializer that operates
THEORY OF OPERATION
from a 12x clock generated by the PLL. The 12 data
bits from each channel are serialized and sent LSB
The ADS528x devices are a family of 8-channel,
first. In addition to serializing the data, the serializer
high-speed, CMOS ADCs. The 12 bits given out by
also generates a 1x clock and a 6x clock. These
each channel are serialized and sent out on a single
clocks are generated in the same way the serialized
pair of pins in LVDS format. All eight channels of the
data are generated, so these clocks maintain perfect
ADS528x operate from a single clock (ADCLK). The
synchronization with the data. The data and clock
sampling clocks for each of the eight channels are
outputs of the serializer are buffered externally using
generated from the input clock using a carefully
LVDS buffers. Using LVDS buffers to transmit data
matched clock buffer tree. The 12x clock required for
externally has multiple advantages, such as a
the serializer is generated internally from ADCLK
reduced number of output pins (saving routing space
using a phase-locked loop (PLL). A 6x and a 1x clock
on the board), reduced power consumption, and
are also output in LVDS format, along with the data,
reduced effects of digital noise coupling to the analog
to enable easy data capture. The ADS528x operates
circuit inside the ADS528x.
from internally-generated reference voltages that are
trimmed to improve to a high level of accuracy.
The ADS528x operates from two sets of supplies and
Trimmed references improve the gain matching
grounds. The analog supply and ground set is
across devices, and provide the option to operate the
identified as AVDD and AVSS, while the digital set is
devices without having to externally drive and route
identified by LVDD and LVSS.
reference lines. The nominal values of REF
T
and
REF
B
are 2.5V and 0.5V, respectively. The
ANALOG INPUT
references are internally scaled down differentially by
a factor of 2. This scaling results in a differential input
The analog input consists of a switched-capacitor
of –1V to correspond to the zero code of the ADC,
based, differential sample-and-hold architecture. This
and a differential input of +1V to correspond to the
differential topology results in very good ac
full-scale code (4095 LSB). V
CM
(the common-mode
performance even for high input frequencies at high
voltage of REF
T
and REF
B
) is also made available
sampling rates. The IN
N
and IN
P
pins must be
externally through a pin, and is nominally 1.5V.
externally biased around a common-mode voltage of
1.5V, available on V
CM
. For a full-scale differential
The ADC employs a pipelined converter architecture
input, each input pin (IN
N
and IN
P
) must swing
that consists of a combination of multi-bit and single-
symmetrically between V
CM
+ 0.5V and V
CM
– 0.5V,
bit internal stages. Each stage feeds its data into the
resulting in a 2V
PP
differential input swing. The
digital error correction logic, ensuring excellent
maximum input peak-to-peak differential swing is
differential linearity and no missing codes at the 12-
determined to be the difference between the internal
bit level.
reference voltages REF
T
(2.5V nominal) and REF
B
(0.5V nominal). Figure 34 illustrates the model of the
input driving circuit.
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