Datasheet

0.64
0.62
0.60
0.58
0.56
0.54
0.52
StandardDeviation(LSB)
0
1 2
3
4
5 6
OverloadSignalAmplitude(dBFS)
f =65MSPS
f =5MHz
S
IN
StandardDeviationof
2ndPointAfterOverload
StandardDeviationof
1stPointAfterOverload
t
S
16384t (Group1)
S
Set1,Point1(of16) Set1,Point2(of16)
Firstpointafteroverload(Set1)
Firstpointafteroverload(Set2)
Secondpointafteroverload(Set2)
Secondpointafteroverload(Set1)
Overload
Amplitude
NOTES:
Inputsinewavephaseisrepetitiveover16384clockcycles.
16suchrepetitivegroups(of16384clockcycles)arecaptured–atotalof262,144points.
Standarddeviationofeverysetof areanalyzedoverthe16groups.
Worstcaseofallsuchstandarddeviationsareplottedinthegraphs.
firstandsecondpointsafteroverload
+FS
-FS
0.70
0.68
0.66
0.64
0.62
0.60
0.58
0.56
0.54
0.52
0.50
StandardDeviation(inLSB)
0
1 2
3
4
5 6
OverloadSignalAmplitude(dBFS)
f =50MSPS
f =5MHz
S
IN
StandardDeviationof
2ndPointAfterOverload
StandardDeviationof
1stPointAfterOverload
170
130
110
90
70
30
ClockFrequency(MSPS)
5
75
I ,I (mA)
AVDD
LVDD
352515 45
I
LVDD
I
AVDD
ZeroInputonAllChannels
InternalReferenceMode
150
55
50
65
0.75
0.55
0.35
0.15
-0.05
-0.25
-0.65
Code(LSB)
0 4096
INL(LSB)
30722048 25601536 35841024512
-0.45
f =65MSPS
f =5MHz
S
IN
0.35
0.25
0.15
0.05
-0.05
-0.15
-0.35
Code(LSB)
0 4096
DNL(LSB)
30722048 25601536 35841024512
-0.25
f =65MSPS,f =5MHz
S IN
ADS5281
ADS5282
www.ti.com SBAS397I –DECEMBER 2006–REVISED JUNE 2012
TYPICAL CHARACTERISTICS (continued)
At T
A
= +25°C, AVDD = +3.3V, LVDD = 1.8V, clock frequency = 65MSPS, differential clock mode, 1V
PP
clock amplitude, 50%
clock duty cycle, input frequency = 10MHz, –1dBFS differential analog input, 0dB digital gain setting, 1.5V analog input
common-mode, low-frequency noise suppression = off, internal reference mode, I
SET
resistor = 56.2kΩ, and LVDS buffer
current setting = 3.5mA, unless otherwise noted.
INTEGRAL NONLINEARITY DIFFERENTIAL NONLINEARITY
Figure 28. Figure 29.
AVDD AND LVDD POWER-SUPPLY CURRENTS
vs CLOCK FREQUENCY OVERLOAD RECOVERY AT 50MSPS
Figure 30. Figure 31.
OVERLOAD RECOVERY AT 65MSPS
Figure 32. Figure 33. Overload Recovery
Copyright © 2006–2012, Texas Instruments Incorporated 31