Datasheet

0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.5
Code(LSB)
0 4096
INL(LSB)
30722048 25601536 35841024512
-0.4
-0.3
f =50MSPS
f =5MHz
S
IN
0.35
0.25
0.15
0.05
-0.05
-0.15
-0.35
Code(LSB)
0 4096
DNL(LSB)
30722048 25601536 35841024512
-0.25
f =50MSPS
f =5MHz
S
IN
60
50
40
30
20
10
0
CodeBin(LSB)
2049
Occurrence(%)
20532051 2054
f =65MSPS
S
2050 2052
0% 0%
0.37% 0.28%
51.92%
47.43%
10
-10
-30
-50
-70
-90
-110
-130
-150
InputFrequency(MHz)
0 2 20
Amplitude(dB)
1816141210864
f =65MHz
f =10MHz( 7dBFS)
f =16.1MHz( 7dBFS)
IMD= 97dBFS
-
-
-
S
1
2
95
90
85
80
75
70
65
60
ClockDutyCycle(%)
35
65
DynamicPerformance(SNR,SFDR)
504540 55
SNR(dBFS)
SFDR(dBc)
f =65MHz
f =10MHz
S
IN
60
95
85
80
75
70
60
ClockDutyCycle(%)
20
80
DynamicPerformance(SNR,SFDR)
504030 60
SNR(dBFS)
SFDR(dBc)
f =65MHz
f =10MHz
S
IN
90
70
65
ADS5281
ADS5282
SBAS397I –DECEMBER 2006–REVISED JUNE 2012 www.ti.com
TYPICAL CHARACTERISTICS (continued)
At T
A
= +25°C, AVDD = +3.3V, LVDD = 1.8V, clock frequency = 65MSPS, differential clock mode, 1V
PP
clock amplitude, 50%
clock duty cycle, input frequency = 10MHz, –1dBFS differential analog input, 0dB digital gain setting, 1.5V analog input
common-mode, low-frequency noise suppression = off, internal reference mode, I
SET
resistor = 56.2kΩ, and LVDS buffer
current setting = 3.5mA, unless otherwise noted.
DYNAMIC PERFORMANCE vs CLOCK DUTY CYCLE, DCC DYNAMIC PERFORMANCE vs CLOCK DUTY CYCLE, DCC
DISABLED ENABLED
Figure 22. Figure 23.
HISTOGRAM OF OUTPUT CODE FOR ZERO INPUT INTERMODULATION DISTORTION
Figure 24. Figure 25.
INTEGRAL NONLINEARITY DIFFERENTIAL NONLINEARITY
Figure 26. Figure 27.
30 Copyright © 2006–2012, Texas Instruments Incorporated