Datasheet

ADS5281
ADS5282
www.ti.com SBAS397I –DECEMBER 2006–REVISED JUNE 2012
RECOMMENDED OPERATING CONDITIONS
(1)
ADS528x
PARAMETER MIN TYP MAX UNIT
SUPPLIES, ANALOG INPUTS, AND REFERENCE VOLTAGES
AVDD Analog supply voltage 3.0 3.3 3.6 V
LVDD Digital supply voltage 1.7 1.8 1.9 V
Differential input voltage range 2 V
PP
Input common-mode voltage V
CM
± 0.05 V
REF
T
External reference mode 2.5 V
REF
B
External reference mode 0.5 V
CLOCK INPUTS
ADCLK input sample rate 1/ t
C
10 50, 65 MSPS
Input clock amplitude differential (V
CLKP
–V
CLKN
) peak-to-peak
Sine wave, ac-coupled 3.0 V
PP
LVPECL, ac-coupled 1.6 V
PP
LVDS, ac-coupled 0.7 V
PP
Input clock CMOS, single-ended (V
CLKP
)
V
IL
0.6 V
V
IH
2.2 V
Input clock duty cycle 50 %
DIGITAL OUTPUTS
ADCLK
P
and ADCLK
N
outputs (LVDS) 10 1x (sample rate) 50, 65 MHz
LCLK
P
and LCLK
N
outputs (LVDS) 60 6x (sample rate) 300, 390 MHz
C
LOAD
Maximum external capacitance from each pin to LVSS 5 pF
R
LOAD
Differential load resistance between the LVDS output pairs 100 Ω
T
A
Operating free-air temperature –40 +85 °C
(1) All conditions are common to the ADS528x family.
INITIALIZATION REGISTERS
After the device has been powered up, the following registers must be written to (in the exact order listed below) through the
serial interface as part of an initialization sequence.
(1)
ADDRESS (hex) DATA (hex)
Initialization Register 1
(1)
03 0002
Initialization Register 2
(1)
01 0010
Initialization Register 3
(1)
C7 8001
Initialization Register 4
(1)
DE 01C0
(1) It is no longer necessary to write these initialization registers. However, customers who have already included them in their software can
continue to use them. Programming these registers does not affect device performance.
If the analog input is ac-coupled, the following registers must be written to in the order listed below.
ADDRESS (hex) DATA (hex)
Initialization Register 1 01 0010
Initialization Register 5 E2 00C0
To disable the PLL configuration switching (especially useful in systems where a system-level timing calibration is done once
after power-up), the following registers must be written to in the order listed below. Also, see section PLL Operation Across
Sampling Frequency.
ADDRESS (hex) DATA (hex)
For 10 ≤ Fs ≤ 25
(1)
E3 0060
For 15 ≤ Fs = ≤ 45
(1)
E3 00A0
(1) where Fs = sampling clock frequency
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