Datasheet

EN_SDR='1',FALL_SDR='0'
EN_SDR='1',FALL_SDR='1'
ADCLK
P
LCLK
P
OUT
P
ADCLK
P
LCLK
P
OUT
P
ADS5281
ADS5282
www.ti.com SBAS397I –DECEMBER 2006–REVISED JUNE 2012
In addition to programming the phase of LCLK in the DDR mode, the device can also be made to operate in SDR
mode by setting the EN_SDR bit to '1'. In this mode, the bit clock (LCLK) is output at 12x times the input clock, or
twice the rate as in DDR mode. Depending on the state of FALL_SDR, LCLK may be output in either of the two
manners shown in Figure 3. As can be seen in Figure 3, only the LCLK rising (or falling) edge is used to capture
the output data in SDR mode.
Figure 3. SDR Interface Modes
The SDR mode does not work well beyond 40MSPS because the LCLK frequency becomes very high.
DATA OUTPUT FORMAT MODES
The ADC output, by default, is in straight offset binary mode. Programming the BTC_MODE bit to '1' inverts the
MSB, and the output becomes binary two's complement mode.
Also by default, the first bit of the frame (following the rising edge of ADCLK
P
) is the LSB of the ADC output.
Programming the MSB_FIRST mode inverts the bit order in the word, and the MSB is output as the first bit
following the ADCLK
P
rising edge.
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