Datasheet

PHASE_DDR<1:0>='00'
PHASE_DDR<1:0>='01'
PHASE_DDR<1:0>='10'
PHASE_DDR<1:0>='11'
ADCLK
P
LCLK
P
OUT
P
ADCLK
P
LCLK
P
OUT
P
ADCLK
P
LCLK
P
OUT
P
ADCLK
P
LCLK
P
OUT
P
ADCLK
P
LCLK
P
OUT
P
ADS5281
ADS5282
SBAS397I –DECEMBER 2006–REVISED JUNE 2012 www.ti.com
BIT CLOCK PROGRAMMABILITY
The output interface of the ADS528x is normally a DDR interface, with the LCLK rising edge and falling edge
transitions in the middle of alternate data windows. This default phase is shown in Figure 1.
Figure 1. Default Phase of LCLK
The phase of LCLK can be programmed relative to the output frame clock and data using bits
PHASE_DDR<1:0>. The LCLK phase modes are shown in Figure 2.
Figure 2. Phase Programmability Modes for LCLK
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