Datasheet

VREF =1.5V -
B
V
CM
1.5V
VREF =1.5V+
T
V
CM
1.5V
ADS5281
ADS5282
www.ti.com SBAS397I –DECEMBER 2006–REVISED JUNE 2012
CLOCK, REFERENCE, AND DATA OUTPUT MODES
ADDRESS
IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME
1 X DIFF_CLK
1 X EN_DCC
42
1 X EXT_REF_VCM
1 X X PHASE_DDR<1:0>
1 1 X BTC_MODE
1 1 X MSB_FIRST
46
1 1 X EN_SDR
1 X 1 1 FALL_SDR
INPUT CLOCK
The ADS528x is configured by default to operate with a single-ended input clock—CLK
P
is driven by a CMOS
clock and CLK
N
is tied to '0'. However, by programming DIFF_CLK to '1', the device can be made to work with a
differential input clock on CLK
P
and CLK
N
. Operating with a low-jitter differential clock usually gives better SNR
performance, especially at input frequencies greater than 30MHz.
In cases where the duty cycle of the input clock falls outside the 45% to 55% range, it is recommended to enable
an internal duty cycle correction circuit. This enabling is done by setting the EN_DCC bit to '1'.
EXTERNAL REFERENCE
The ADS528x can be made to operate in external reference mode by pulling the INT/EXT pin to '0'. In this mode,
the REF
T
and REF
B
pins should be driven with voltage levels of 2.5V and 0.5V, respectively, and must have
enough drive strength to drive the switched capacitance loading of the reference voltages by each ADC. The
advantage of using the external reference mode is that multiple ADS528x units can be made to operate with the
same external reference, thereby improving parameters such as gain matching across devices. However, in
applications that do not have an available high drive, differential external reference, the ADS528x can still be
driven with a single external reference voltage on the V
CM
pin. When EXT_REF_VCM is set as '1' (and the
INT/EXT pin is set to '0'), the V
CM
pin is configured as an input pin, and the voltages on REF
T
and REF
B
are
generated as shown in Equation 1 and Equation 2.
(1)
(2)
Copyright © 2006–2012, Texas Instruments Incorporated 23