Datasheet

ADS5281
ADS5282
SBAS397I –DECEMBER 2006–REVISED JUNE 2012 www.ti.com
Table 4. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE
(1) (2) (3) (4)
(continued)
ADDRESS
IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME DESCRIPTION DEFAULT
Single-
1 X DIFF_CLK Differential clock mode.
ended clock
Enables the duty-cycle correction
1 X EN_DCC Disabled
circuit.
External
42
Drives the external reference reference
1 X EXT_REF_VCM
mode through the V
CM
pin. drives REF
T
and REF
B
Controls the phase of LCLK
1 X X PHASE_DDR<1:0> 90 degrees
output relative to data.
0 X PAT_DESKEW Enables deskew pattern mode. Inactive
45
X 0 PAT_SYNC Enables sync pattern mode. Inactive
Binary two's complement format Straight
1 1 X BTC_MODE
for ADC output. offset binary
Serialized ADC output comes LSB-first
1 1 X MSB_FIRST
out MSB-first. output
Enables SDR output mode
DDR output
46
1 1 X EN_SDR (LCLK becomes a 12x input
mode
clock).
Controls whether the LCLK rising Rising edge
or falling edge comes in the of LCLK in
1 X 1 1 FALL_SDR
middle of the data window when middle of
operating in SDR output mode. data window
SUMMARY OF FEATURES
POWER IMPACT (relative to default)
FEATURES DEFAULT SELECTION AT f
S
= 65MSPS
ANALOG FEATURES
Internal or external reference Internal reference mode uses approximately 23mW more
N/A Pin
(driven on the REF
T
and REF
B
pins) power on AVDD
External reference driven on the
Off Register 42 Approximately 9mW less power on AVDD
V
CM
pin
Duty cycle correction circuit Off Register 42 Approximately 7mW more power on AVDD
With zero input to the ADC, low-frequency noise suppression
Low-frequency noise suppression Off Register 14 causes digital switching at f
S
/2, thereby increasing LVDD
power by approximately 7mW/channel
Differential clock mode uses approximately 7mW more power
Single-ended or differential clock Single-ended Register 42
on AVDD
Refer to the Power-Down Modes section in the Electrical
Power-down mode Off Pin and register 0F
Characteristics table
DIGITAL FEATURES
Programmable digital gain (0dB to Registers 2A and
0dB No difference
12dB) 2B
Straight offset or BTC output Straight offset Register 46 No difference
Swap polarity of analog input pins Off Register 24 No difference
LVDS OUTPUT PHYSICAL LAYER
LVDS internal termination Off Register 12 Approximately 7mW more power on AVDD
LVDS current programmability 3.5mA Register 11 As per LVDS clock and data buffer current setting
LVDS OUTPUT TIMING
LSB- or MSB-first output LSB-first Register 46 No difference
SDR mode uses approximately 2mW more power on LVDD
DDR or SDR output DDR Register 46
(at f
S
= 30MSPS)
Refer to
LCLK phase relative to data output Register 42 No difference
Figure 1
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