Datasheet

t
1
t
2
t
3
AVDD(3Vto3.6V)
LVDD(1.7Vto1.9V)
High-Level
RESET
(1.4Vto3.6V)
High-Level
CS
(1.4Vto3.6V)
DeviceReadyfor
SerialRegisterWrite
(2)
DeviceReadyfor
DataConversion
StartofClock
AVDD
LVDD
RESET
CS
ADCLK
t
4
t
7
t
5
t
8
t
6
ADS5281
ADS5282
SBAS397I –DECEMBER 2006–REVISED JUNE 2012 www.ti.com
LVDS OUTPUT TIMING CHARACTERISTICS
TIMINGS WHEN USING REGISTER 0xE3
(2)
At 40 MSPS
PARAMETER
(1)
TEST CONDITIONS
MIN TYP MAX
Data setup time Data valid
(3)
to zero-crossing of LCLKp 0.60
Data hold time Zero-crossing of LCLKP to data becoming invalid
(3)
0.92
Input clock (ADCLK) rising edge cross-over to output clock (ADCLK) rising edge
Clock propagation delay 8 12 14.6
crossover
(1) Only the setup time, hold time and clock propagation delay parameters are affected. Rest of the parameters are same as given in
previous two tables.
(2) Only timing specifications for 40MSPS are affected when using register 0xE3 (as specified in the recommended operating table section).
The timing specifications for other clock frequencies are same as given in previous two tables.
(3) Data valid refers to logic high of +100mV and logic low of –100mV.
RECOMMENDED POWER-UP SEQUENCING AND RESET TIMING
10μs < t
1
< 50ms, 10μs < t
2
< 50ms, –10ms < t
3
< 10ms, t
4
> 10ms, t
5
> 100ns, t
6
> 100ns, t
7
> 10ms, and t
8
> 100μs.
(1) The AVDD and LVDD power on sequence does not matter as long as –10ms < t
3
< 10ms. Similar considerations apply while shutting
down the device.
(2) Write initialization registers listed in the Initialization Registers table.
14 Copyright © 2006–2012, Texas Instruments Incorporated