Datasheet

ADS5281
ADS5282
SBAS397I –DECEMBER 2006–REVISED JUNE 2012 www.ti.com
Table 3. PIN DESCRIPTIONS: QFN-64 (continued)
PIN NAME DESCRIPTION PIN NUMBER # OF PINS
IN5
P
Positive differential input signal, channel 5 38 1
IN6
N
Negative differential input signal, channel 6 42 1
IN6
P
Positive differential input signal, channel 6 41 1
IN7
N
Negative differential input signal, channel 7 45 1
IN7
P
Positive differential input signal, channel 7 44 1
IN8
N
Negative differential input signal, channel 8 48 1
IN8
P
Positive differential input signal, channel 8 47 1
INT/EXT Internal/external reference mode select input 56 1
I
SET
Bias pin—56.2kΩ to ground 51 1
LCLK
N
LVDS bit clock (6X)—negative output 26 1
LCLK
P
LVDS bit clock (6X)—positive output 25 1
LVDD Digital and I/O power supply, 1.8V 35 1
LVSS Digital ground 12, 14, 36 3
OUT1
N
LVDS channel 1—negative output 16 1
OUT1
P
LVDS channel 1—positive output 15 1
OUT2
N
LVDS channel 2—negative output 18 1
OUT2
P
LVDS channel 2—positive output 17 1
OUT3
N
LVDS channel 3—negative output 20 1
OUT3
P
LVDS channel 3—positive output 19 1
OUT4
N
LVDS channel 4—negative output 22 1
OUT4
P
LVDS channel 4—positive output 21 1
OUT5
N
LVDS channel 5—negative output 28 1
OUT5
P
LVDS channel 5—positive output 27 1
OUT6
N
LVDS channel 6—negative output 30 1
OUT6
P
LVDS channel 6—positive output 29 1
OUT7
N
LVDS channel 7—negative output 32 1
OUT7
P
LVDS channel 7—positive output 31 1
OUT8
N
LVDS channel 8—negative output 34 1
OUT8
P
LVDS channel 8—positive output 33 1
PD Power-down input 13 1
REF
B
Negative reference input/output 54 1
REF
T
Positive reference input/output 55 1
RESET Active low RESET input 64 1
SCLK Serial clock input 63 1
SDATA Serial data input 62 1
TP Test pin, do not use 52 1
V
CM
Common-mode output pin, 1.5V output 53 1
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