Datasheet

ADCLK
6X ADCLK
SERIAL DATA
1X ADCLK
LCLK
P
LCLK
N
OUT
P
OUT
N
ADCLK
P
ADCLK
N
Sample n data
Input
t
PROP
t
D
(A)
Sample n
Sample n + 6
D3 D4 D5 D6 D7 D8 D9D0 D1 D2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9D11D10
1
t
SAMPLE
t
S
2
D11D10
D1D0
6.5 Clock Cycles
NOTE: Serial data bit format shown in LSB first mode.
t
1
t
3
t
5
t
6
t
4
t
7
t
8
t
2
AVDD (3V to 3.6V)
LVDD (3V to 3.6V)
Device Ready
For ADC Operation
Device Ready
For ADC Operation
Device Ready
For Serial Register Write
Start of Clock
AVDD
LVDD
RESET
CS
ADCLK
NOTE: 10
µ
s < t
1
< 50ms; 10
µ
s < t
2
< 50ms;
10ms < t
3
< 10ms; t
4
> 10ms; t
5
> 100ns; t
6
> 100ns; t
7
> 10ms; and t
8
> 100
µ
s.
ADS5272
SBAS324C JUNE 2004 REVISED JANUARY 2009 ......................................................................................................................................................
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LVDS TIMING DIAGRAM (PER ADC CHANNEL)
RECOMMENDED POWER-UP SEQUENCING AND RESET TIMING
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