Datasheet

ELECTRICAL CHARACTERISTICS
ADS5272
SBAS324C – JUNE 2004 – REVISED JANUARY 2009 ...................................................................................................................................................... www.ti.com
T
MIN
= – 40 ° C and T
MAX
= +85 ° C. Typical values are at T
A
= +25 ° C, clock frequency = maximum specified, 50% clock duty
cycle, AVDD = 3.3V, LVDD = 3.3V, – 1dBFS, I
SET
= 56.2k Ω , internal voltage reference, and LVDS buffer current at 3.5mA per
channel, unless otherwise noted. All values are applicable after the device has been reset.
ADS5272
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
DC ACCURACY
No Missing Codes Tested
DNL Differential Nonlinearity f
IN
= 5MHz – 0.95 ± 0.31 +1.0 LSB
INL Integral Nonlinearity f
IN
= 5MHz – 2.5 ± 0.41 +2.5 LSB
Offset Error
(1)
– 0.75 +0.75 %FS
Offset Temperature Coefficient ± 6 ppm/ ° C
Fixed Attenuation in Channel
(2)
1.5 %FS
Fixed Attenuation Matching Across Channels 0.01 0.2 dB
Gain Error/Reference Error
(3)
VREF
T
– VREF
B
– 2.5 ± 1.0 +2.5 %FS
Gain Error Temperature Coefficient ± 20 ppm/ ° C
POWER REQUIREMENTS
(4)
Internal Reference
Power Dissipation Analog Only (AVDD) 785 848 mW
Output Driver (LVDD) 198 224 mW
Total Power Dissipation 983 1072 mW
External Reference
Power Dissipation Analog Only (AVDD) 719 mW
Output Driver (LVDD) 198 mW
Total Power Dissipation 917 mW
Total Power-Down Clock Running 94 149 mW
REFERENCE VOLTAGES
VREF
T
Reference Top (internal) 1.9 1.95 2.0 V
VREF
B
Reference Bottom (internal) 0.9 0.95 1.0 V
V
CM
Common-Mode Voltage 1.4 1.45 1.5 V
V
CM
Output Current
(5)
± 50mV Change in Voltage ± 2.0 mA
VREF
T
Reference Top (external) 1.825 1.95 2.0 V
VREF
B
Reference Bottom (external) 0.9 0.95 1.075 V
External Reference Common-Mode V
CM
± 50mV V
External Reference Input Current
(6)
1.0 mA
(1) Offset error is the deviation of the average code from mid-code with – 1dBFS sinusoid from ideal mid-code (2048). Offset error is
expressed in terms of % of full-scale.
(2) Fixed attenuation in the channel arises due to a fixed attenuation in the sample-and-hold amplifier. When the differential voltage at the
analog input pins are changed from – V
REF
to +V
REF
, the swing of the output code is expected to deviate from the full-scale code
(4096LSB) by the extent of this fixed attenuation. NOTE: V
REF
is defined as (REF
T
– REF
B
).
(3) The reference voltages are trimmed at production so that (VREF
T
– VREF
B
) is within ± 25mV of the ideal value of 1V. This specification
does not include fixed attenuation.
(4) Supply current can be calculated from dividing the power dissipation by the supply voltage of 3.3V.
(5) V
CM
provides the common-mode current for the inputs of all eight channels when the inputs are ac-coupled. The V
CM
output current
specified is the additional drive of the V
CM
buffer if loaded externally.
(6) Average current drawn from the reference pins in the external reference mode.
4 Submit Documentation Feedback Copyright © 2004 – 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS5272