Datasheet

LVDS BUFFERS
NOISE COUPLING ISSUES
External
Termination
Resistor
OUT
P
High
Low
OUT
N
Low
High
ADS5272
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has 50% duty cycle. The input sampling instant, takes the output data from each channel and
however, is determined by the rising edge of the serializes it into a single data stream. For a clock
external clock and is not affected by jitter in the PLL. frequency of 65MHz, the data rate output of the
In addition to generating a 50% duty cycle clock for serializer is 780Mbps. The data comes out LSB first,
the ADC, the PLL also generates a 12x clock that is with a register programmability that allows it to revert
used by the serializer to convert the parallel data from to MSB first. The serializer also transmits a 1x clock
the ADC to a serial stream of bits. and a 6x clock. The 6x clock (denoted as
LCLK
P
/LCLK
N
) is meant to synchronize the capture of
The use of the PLL automatically dictates the
the LVDS data.
minimum sample rate to be about 20MSPS. The PLL
also requires the input clock to be free-running. If the Deskew mode can be enabled as well, using a
input clock is momentarily stopped (for a duration of register setting. This mode gives out a data stream of
less than 300ns) then the PLL would require alternate 0s and 1s and can be used determine the
approximately 10 µ s to lock back to the input clock relative delay between the 6x clock and the output
frequency. data for optimum capture. A 1x clock is also
generated by the serializer and transmitted through
the LVDS buffer. The 1x clock (referred to as
ADCLK
P
/ADCLK
N
) is used to determine the start of
The LVDS buffer has two current sources, as shown
the 12-bit data frame. Sync mode (enabled through a
in Figure 37 . OUT
P
and OUT
N
are loaded externally
register setting) gives out a data of six 0s followed by
by a resistive load that is ideally about 100 Ω .
six 1s. Using this mode, the 1x clock can be used to
Depending on whether the data is 0 or 1, the currents
determine the start of the data frame. In addition to
are directed in one direction or the other through the
the deskew mode pattern and the sync mode pattern,
resistor. The LVDS buffer has four current settings.
a custom pattern can be defined by the user and
The default current setting is 3.5mA, and provides a
output from the LVDS buffer. The LVDS buffers are
differential drop of about ± 350mV across the 100 Ω
tri-stated in the power-down mode. The LVDS outputs
resistor.
are weakly forced to 1.2V through 10k Ω resistors
(from each output pin to 1.2V).
The single-ended output impedance of the LVDS
drivers is very high because they are current-source
driven. If there are excessive reflections from the
receiver, it might be necessary to place a 100 Ω
High-speed mixed signals are sensitive to various
termination resistor across the outputs of the LVDS
types of noise coupling. One of the main sources of
drivers to minimize the effect of reflections. In such a
noise is the switching noise from the serializer and
situation, the output current of the LVDS drivers can
the output buffers. Maximum care is taken to isolate
be increased to regain the output swing.
these noise sources from the sensitive analog blocks.
As a starting point, the analog and digital domains of
the chip are clearly demarcated. AVDD and AVSS
are used to denote the supplies for the analog
sections, while LVDD and LVSS are used to denote
the digital supplies. Care is taken to ensure that there
is minimal interaction between the supply sets within
the device. The extent of noise coupled and
transmitted from the digital to the analog sections
depends on the following:
1. The effective inductances of each of the
supply/ground sets.
2. The isolation between the digital and analog
supply/ground sets.
Smaller effective inductance of the supply/ground
pins leads to better suppression of the noise. For this
reason, multiple pins are used to drive each
supply/ground. It is also critical to ensure that the
impedances of the supply and ground lines on board
are kept to the minimum possible values. Use of
ground planes in the board as well as large
Figure 37. LVDS Buffer
decoupling capacitors between the supply and
ground lines are necessary to get the best possible
The LVDS buffer receives data from a serializer that
SNR from the device.
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