Datasheet

REFERENCE CIRCUIT DESIGN
CLOCKING
REF
T
REF
B
0.1
µ
F 2.2
µ
F
> 2
Ω
> 2
Ω
2.2
µ
F 0.1
µ
F
ADS5272
ADS5272
SBAS324C – JUNE 2004 – REVISED JANUARY 2009 ...................................................................................................................................................... www.ti.com
reference voltages. This mode involves forcing REF
T
and REF
B
externally. In this mode, the internal
The digital beam-forming algorithm relies heavily on
reference buffer is tri-stated. Since the switching
gain matching across all receiver channels. A typical
current for the eight ADCs come from the externally
system would have about 12 octal ADCs on the
forced references, it is possible for the performance
board. In such a case, it is critical to ensure that the
to be slightly less than when the internal references
gain is matched, essentially requiring the reference
are used. It should be noted that in this mode, V
CM
voltages seen by all the ADCs to be the same.
and I
SET
continue to be generated from the internal
Matching references within the eight channels of a
bandgap voltage, as in the internal reference mode. It
chip is done by using a single internal reference
is therefore important to ensure that the
voltage buffer. Trimming the reference voltages on
common-mode voltage of the externally forced
each chip during production ensures the reference
reference voltages matches to within 50mV of V
CM
.
voltages are well matched across different chips.
The state of the reference voltages during various
combinations of PD and INT/ EXT is shown in
All bias currents required for the internal operation of
Table 1 .
the device are set using an external resistor to
ground at pin I
SET
. Using a 56.2k Ω resistor on I
SET
Table 1. State of Reference Voltages for Various
generates an internal reference current of 20 µ A. This
Combinations of PD and INT/ EXT
current is mirrored internally to generate the bias
current for the internal blocks. Using a larger external
PD 0 0 1 1
resistor at I
SET
reduces the reference bias current and
INT/ EXT 0 1 0 1
thereby scales down the device operating power.
REF
T
Tri-State 1.95V Tri-State Tri-State
However, it is recommended that the external resistor
REF
B
Tri-State 0.95V Tri-State Tri-State
be within 10% of the specified value of 56.2k Ω so
that the internal bias margins for the various blocks
V
CM
1.45V 1.45V Tri-State
(1)
Tri-State
(1)
are proper.
(1) Weak pull-down (approximately 5k Ω ) to ground.
Buffering the internal bandgap voltage also generates
a voltage called V
CM
, which is set to the midlevel of
REF
T
and REF
B
, and is accessible on a pin. It is
meant as a reference voltage to derive the input
The eight channels on the chip operate from a single
common-mode in case the input is directly coupled. It
ADCLK input. To ensure that the aperture delay and
can also be used to derive the reference
jitter are same for all the channels, a clock tree
common-mode voltage in the external reference
network is used to generate individual sampling
mode.
clocks to each channel. The clock paths for all the
channels are matched from the source point all the
When using the internal reference mode, a 2 Ω
way to the sample-and-hold amplifier. This ensures
resistor should be added between the reference pins
that the performance and timing for all the channels
(REF
T
and REF
B
) and the decoupling capacitor, as
are identical. The use of the clock tree for matching
shown in Figure 36 . If the device is used in the
introduces an aperture delay, which is defined as the
external reference mode, this 2 Ω resistor is not
delay between the rising edge of ADCLK and the
required.
actual instant of sampling. The aperture delays for all
the channels are matched to the best possible extent.
However, a mismatch of ± 20ps ( ± 3 σ ) could exist
between the aperture instants of the eight ADCs
within the same chip. However, the aperture delays of
ADCs across two different chips can be several
hundred picoseconds apart. Another critical
specification is the aperture jitter that is defined as
the uncertainty of the sampling instant. The gates in
the clock path are designed to provide an rms jitter of
approximately 1ps.
Ideally, the input ADCLK should have a 50% duty
cycle. However, while routing ADCLK to different
components onboard, the duty cycle of the ADCLK
reaching the ADS5272 could deviate from 50%. A
smaller (or larger) duty cycle reduces the time
Figure 36. Internal Reference Mode
available for sample or hold phases of each circuit,
and is therefore not optimal. For this reason, the
The device also supports the use of external
internal PLL is used to generate an internal clock that
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