Datasheet

INPUT OVER-VOLTAGE RECOVERY
5nH
to 9nH
3.2pF
to 4.8pF
IN OUT
IN
P
1.5pF to
2.5pF
1
Ω
500
Ω
to 720
Ω
15
Ω
to 25
Ω
500
Ω
to 720
Ω
5nH
to 9nH
IN
N
1.5pF to
2.5pF
1
Ω
15
Ω
to 25
Ω
60
Ω
to 120
Ω
1.5pF
to 1.9pF
IN OUT
3.2pF
to 4.8pF
IN OUT
15
Ω
to 25
Ω
15
Ω
to 25
Ω
60
Ω
to 120
Ω
IN OUT
IN
OUT
15
Ω
to 35
Ω
IN OUT
IN OUT
OUT
P
OUT
N
Switches that are ON
in SAMPLE phase.
Switches that are ON
in HOLD phase.
ADS5272
www.ti.com ...................................................................................................................................................... SBAS324C – JUNE 2004 – REVISED JANUARY 2009
Figure 35 shows a detailed RLC model of the over-voltage pulse input of twice the amplitude of a
sample-and-hold circuit. The circuit operates in two full-scale pulse is expected to be within three clock
phases. In the sample phase, the input is sampled on cycles when the input switches from overload to zero
two capacitors that are nominally 4pF. The sampling signal. All of the amplifiers in the SHA and ADC are
circuit consists of a low-pass RC filter at the input to specially designed for excellent recovery from an
filter out noise components that might be differentially overload signal.
coupled on the input pins. The next phase is the hold
In most applications, the ADC inputs are driven with
phase wherein the voltage sampled on the capacitors
differential sinusoidal inputs. While the pulse-type
is transferred (using the amplifier) to a subsequent
signal remains at peak overload conditions
pipeline ADC stage.
throughout its HIGH state, the sinusoid signal only
attains peak overload intermittently, at its minima and
maxima. This condition is much less severe for the
ADC input and the recovery of the ADC output (to 1%
The differential full-scale range supported by the
of full-scale around the expected code). This typically
ADS5272 is nominally 2.03V. The ADS5272 is
happens within the second clock when the input is
specially designed to handle an over-voltage
driven with a sinusoid of amplitude equal to twice that
condition where the differential peak-to-peak voltage
of the ADC differential full-scale range.
can exceed up to twice the ADC full-scale range. If
the input common-mode is not considerably off from
V
CM
during overload (less than 300mV around the
nominal value of 1.45V), recovery from an
Figure 35. Overall Structure of the Sample-and-Hold Circuit
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