Datasheet
ABSOLUTE MAXIMUM RATINGS
(1)
ADS5272
SBAS324C – JUNE 2004 – REVISED JANUARY 2009 ......................................................................................................................................................
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
SPECIFIED
PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE-LEAD
(2)
DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY
ADS5272IPFP Tray, 96
ADS5272 HTQFP-80 PFP – 40 ° C to +85 ° C ADS5272IPFP
ADS5272IPFPT Tape and Reel, 250
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com .
(2) Thermal pad size: 4.69mm × 4.69mm (min), 6.20mm × 6.20mm (max).
Supply Voltage Range, AVDD – 0.3V to +3.8V
Supply Voltage Range, LVDD – 0.3V to +3.8V
Voltage Between AVSS and LVSS – 0.3V to +0.3V
Voltage Between AVDD and LVDD – 0.3V to +0.3V
Voltage Applied to External REF Pins – 0.3V to +2.4V
All LVDS Data and Clock Outputs – 0.3V to +2.4V
Analog Input Pins
(2)
– 0.3V to min. [3.3V, (AVDD + 0.3V)]
Digital Input Pins, Set 1 (pins 69, 76-78) – 0.3V to min. [3.9V, (AVDD + 0.3V)]
(3)
Digital Input Pins, Set 2 (pins 16, 45) – 0.3V to min. [3.9V, (LVDD + 0.3V)]
(3)
Operating Free-Air Temperature Range, T
A
– 40 ° C to +85 ° C
Lead Temperature, 1.6mm (1/16 " from case for 10s) +260 ° C
Junction Temperature +105 ° C
Storage Temperature Range – 65 ° C to +150 ° C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
(2) The dc voltage applied on the input pins should not go below – 0.3V. Also, the dc voltage should be limited to the lower of either 3.3V or
(AVDD + 0.3V). If the input can go higher than +3.3V, then a resistor greater than or equal to 25 Ω should be added in series with each
of the input pins. Also, the duty cycle of the overshoot beyond +3.3V should be limited. The overshoot duty cycle can be defined either
as a percentage of the time of overshoot over a clock period, or over the entire device lifetime. For a peak voltage between +3.3V and
+3.5V, a duty cycle up to 10% is acceptable. For a peak voltage between +3.5V and +3.7V, the overshoot duty cycle should not exceed
1%. Any overshoot beyond +3.7V should be restricted to less than 0.1% duty cycle, and never exceed +3.9V.
(3) It is recommended that a series resistor of 1k Ω or greater be used if the digital input pins are tied to AVDD or LVDD.
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