Datasheet

ADS5272
SBAS324C JUNE 2004 REVISED JANUARY 2009 ......................................................................................................................................................
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PIN DESCRIPTIONS
NAME PIN # I/O DESCRIPTION
ADCLK 71 I Data Converter Clock Input
ADCLK
N
42 O Negative LVDS ADC Clock Output
ADCLK
P
41 O Positive LVDS ADC Clock Output
AVDD 1, 7, 14, 47, 54, 60, 63, 70, 75 I Analog Power Supply
AVSS 4, 8, 11, 50, 53, 57, 61, 62, 68, 72-74, 79, 80 I Analog Ground
CS 76 I Chip Select; 0 = Select, 1 = No Select
LVDD 25, 35 I LVDS Power Supply
LVSS 15, 17, 18, 26, 36, 43, 44, 46 I LVDS Ground
IN1
N
3 I Channel 1 Differential Analog Input Low
IN1
P
2 I Channel 1 Differential Analog Input High
IN2
N
6 I Channel 2 Differential Analog Input Low
IN2
P
5 I Channel 2 Differential Analog Input High
IN3
N
10 I Channel 3 Differential Analog Input Low
IN3
P
9 I Channel 3 Differential Analog Input High
IN4
N
13 I Channel 4 Differential Analog Input Low
IN4
P
12 I Channel 4 Differential Analog Input High
IN5
N
49 I Channel 5 Differential Analog Input Low
IN5
P
48 I Channel 5 Differential Analog Input High
IN6
N
52 I Channel 6 Differential Analog Input Low
IN6
P
51 I Channel 6 Differential Analog Input High
IN7
N
56 I Channel 7 Differential Analog Input Low
IN7
P
55 I Channel 7 Differential Analog Input High
IN8
N
59 I Channel 8 Differential Analog Input Low
IN8
P
58 I Channel 8 Differential Analog Input High
INT/ EXT 69 I Internal/External Reference Select; 0 = External, 1 = Internal. Weak pull-up to supply.
I
SET
64 I/O Bias Current Setting Resistor of 56.2k to Ground
LCLK
N
20 O Negative LVDS Clock
LCLK
P
19 O Positive LVDS Clock
OUT1
N
22 O Channel 1 Negative LVDS Data Output
OUT1
P
21 O Channel 1 Positive LVDS Data Output
OUT2
N
24 O Channel 2 Negative LVDS Data Output
OUT2
P
23 O Channel 2 Positive LVDS Data Output
OUT3
N
28 O Channel 3 Negative LVDS Data Output
OUT3
P
27 O Channel 3 Positive LVDS Data Output
OUT4
N
30 O Channel 4 Negative LVDS Data Output
OUT4
P
29 O Channel 4 Positive LVDS Data Output
OUT5
N
32 O Channel 5 Negative LVDS Data Output
OUT5
P
31 O Channel 5 Positive LVDS Data Output
OUT6
N
34 O Channel 6 Negative LVDS Data Output
OUT6
P
33 O Channel 6 Positive LVDS Data Output
OUT7
N
38 O Channel 7 Negative LVDS Data Output
OUT7
P
37 O Channel 7 Positive LVDS Data Output
OUT8
N
40 O Channel 8 Negative LVDS Data Output
OUT8
P
39 O Channel 8 Positive LVDS Data Output
PD 16 I Power-Down; 0 = Normal, 1 = Power-Down. Weak pull-down to ground.
REF
B
66 I/O Reference Bottom Voltage (2 resistor in series with a capacitor 0.1 µ F capacitor to ground)
REF
T
67 I/O Reference Top Voltage (2 resistor in series with a capacitor 0.1 µ F capacitor to ground)
RESET 45 I Reset to Default; 0 = Reset, 1 = Normal. Weak pull-down to ground.
SCLK 78 I Serial Data Clock
SDA 77 I Serial Data input
V
CM
65 O Common-Mode Output Voltage
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