Datasheet
LVDS DIGITAL DATA AND CLOCK OUTPUTS
SWITCHING CHARACTERISTICS
ADS5270
www.ti.com
............................................................................................................................................... SBAS293F – JANUARY 2004 – REVISED JANUARY 2009
Test conditions at I
O
= 3.5mA, R
LOAD
= 100 Ω , and C
LOAD
= 6pF. I
O
refers to the current setting for the LVDS buffer. R
LOAD
is the differential
load resistance between the LVDS pair. C
LOAD
is the effective single-ended load capacitance between each of the LVDS pins and ground.
C
LOAD
includes the receiver input parasitics as well as the routing parasitics. Measurements are done with a 1-inch transmission line of 100 Ω
characteristic impedance between the device and the load. All LVDS specifications are characterized, but not parametrically tested at
production. LCLKOUT refers to (LCLK
P
– LCLK
N
); ADCLKOUT refers to (ADCLK
P
– ADCLK
N
); DATA OUT refers to (OUT
P
– OUT
N
); and
ADCLK refers to the input sampling clock.
PARAMETER CONDITIONS MIN TYP MAX UNITS
DC SPECIFICATIONS
(1)
V
OH
Output Voltage High, OUT
P
or OUT
N
R
LOAD
= 100 Ω ± 1%; See LVDS Timing Diagram , Page 8 1265 1365 1465 mV
V
OL
Output Voltage Low, OUT
P
or OUT
N
R
LOAD
= 100 Ω ± 1% 940 1040 1140 mV
|V
OD
| Output Differential Voltage R
LOAD
= 100 Ω ± 1% 275 325 375 mV
V
OS
Output Offset Voltage
(2)
R
LOAD
= 100 Ω ± 1%; See LVDS Timing Diagram , Page 8 1.1 1.2 1.3 V
R
O
Output Impedance, Differential Normal Operation 13 k Ω
R
O
Output Impedance, Differential Power-Down 20 k Ω
C
O
Output Capacitance
(3)
4 pF
| Δ V
OD
| Change in |V
OD
| Between 0 and 1 R
LOAD
= 100 Ω ± 1% 10 mV
Δ V
OS
Change Between 0 and 1 R
LOAD
= 100 Ω ± 1% 25 mV
ISOUT Output Short-Circuit Current Drivers Shorted to Ground 40 mA
ISOUT
NP
Output Current Drivers Shorted Together 12 mA
DRIVER AC SPECIFICATIONS
ADCLKOUT Clock Duty Cycle
(4)
45 50 55 %
LCLKOUT Duty Cycle
(4)
44 50 56 %
Data Setup Time
(5) (6)
0.7 ns
Data Hold Time
(6) (7)
0.61 ns
LVDS Outputs Rise/Fall Time
(8)
I
O
= 2.5mA 400 ps
I
O
= 3.5mA 180 300 500 ps
I
O
= 4.5mA 230 ps
I
O
= 6.0mA 180 ps
LCLKOUT Rising Edge to ADCLKOUT Rising Edge
(9)
0.74 1.04 1.34 ns
ADCLKOUT Rising Edge to LCLKOUT Falling Edge
(9)
0.74 1.04 1.34 ns
ADCLKOUT Rising Edge to DATA OUT Transition
(9)
– 0.35 0 +0.35 ns
(1) The dc specifications refer to the condition where the LVDS outputs are not switching, but are permanently at a valid logic level 0 or 1.
(2) V
OS
refers to the common-mode of OUT
P
and OUT
N
.
(3) Output capacitance inside the device, from either OUT
P
or OUT
N
to ground.
(4) Measured between zero crossings.
(5) DATA OUT (OUT
P
– OUT
N
) crossing zero to LCLKOUT (LCLK
P
– LCLK
N
) crossing zero.
(6) Data setup and hold time accounts for data-dependent skews, channel-to-channel mismatches, as well as effects of clock jitter within
the device.
(7) LCLKOUT crossing zero to DATA OUT crossing zero.
(8) Measured from – 100mV to +100mV on the differential output for rise time, and +100mV to – 100mV for fall time.
(9) Measured between zero crossings.
T
MIN
= – 40 ° C and T
MAX
= +85 ° C. Typical values are at T
A
= +25 ° C, clock frequency = maximum specified, 50% clock duty cycle,
AVDD = 3.3V, LVDD = 3.3V, – 1dBFS, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
SWITCHING SPECIFICATIONS
t
SAMPLE
25 50 ns
t
D
(A) Aperture Delay 2 4 6.5 ns
Aperture Jitter (uncertainty) 1 ps rms
t
D
(pipeline) Latency 6.5 Cycles
t
PROP
Propagation Delay 3 4.8 6.5 ns
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