Datasheet

Basic Test Procedure

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Figure 4. FFT Plot: 160-MHz Clock, 15.5-MHz Input

• Select the desired channel (that is, Channel A or B) from the Channel Display pull-down menu

• Change the ADC sampling rate to the desired value (that is, 250 M)

• Change the input frequency to the desired value (that is, 15.5M)

• Select Rectangular of windowing option after checking Auto Calculation of Coherent Frequencies

• Set the same frequency of signal generator as ADC Input Target Frequency

• Press the Capture button to initiate a data capture

2.5 ADS42xx Test Procedure

• Switch on the 5-V power supply on the ADC EVM. Verify source current is about 330 mA ±30 mA, with

the clock and TSW1400 connected at EVM default (that is, connected at 250 MHz).

• Connect clock signal at J19 through an appropriate BPF

– Adjust the signal generator amplitude output to 0.6 Vrms to provide approximately 0.8 Vpp at J19

through a BPF with about 5 dB attenuation, plus cable losses.

– Use a high quality, low-phase noise generator for this input to ensure proper device evaluation

• Connect the input signal through an appropriate BPF at either J6 or J3 (Channel A or B, that is, 170

MHz)

– Adjust the frequency of the generator to match the coherent frequency displayed in the TSW1400

GUI

– Select the proper Display Channel on the TSW1400 GUI software that corresponds to the input

connection

– Adjust the signal generator amplitude output to achieve –1 dBFS on FFT plot.

– Use a high quality, low-phase noise generator for this input to ensure proper device evaluation.

• Initiate a capture by pressing the Capture button on the TSW1400 GUI.

ADS42xx EVM SLAU333A–March 2011–Revised June 2013

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