Datasheet

Optional Configurations

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The on-board layout is available for the option of VCXO and crystal BPF. The CDCE72010 comes with a

default configuration See the CDCE72010 data sheet (SCAS858) for details about device default

configuration. With a 10-MHz primary reference at J19 and a 983.04-MHz VCXO on-board, the CDC

outputs a LVCMOS clock at U0P (pin 7) at 245.76 MHz. With a 491.52-MHz VCXO, the CDC outputs a

LVCMOS clock at U0P at 122.88 MHz. The clock goes through an on-board crystal BPF (Y0) and is used

as the input clock to the ADC through SJP6.

3.3 Parallel CMOS Output

The default ADC output is configured as DDR LVDS output on the EVM. The layout provides an option of

1.8-V parallel CMOS output from the ADC. The changes required to modify from DDR LVDS output to

parallel CMOS output are shown in Table 5.

Table 5. Jumper and Component Setting for DDR LVDS Output and Parallel

CMOS Output

Jumper or Component DDR LVDS Output Parallel CMOS

U12 (SN74AVC16T245) DNI Installed

U13 (SN74AVC16T245) DNI Installed

RN5 to RN8 Installed DNI

RN9 to RN12 Installed DNI

JP26 Open Shunt

JP27 Open Shunt

The CMOS output data is output from the EVM board at 40-pin connectors J1 (ch A) and J2 (ch B).

ADS42xx EVM SLAU333A–March 2011–Revised June 2013

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