Datasheet

36
35
34
33
32
31
30
29
28
27
26
25
DRGND
DRVDD
NC
NC
NC
NC
RESET
SCLK
SDATA
SEN
AVDD
AGND
D10_D11_P
VCM
D10_D11_M
AGND
D8_D9_P
INP
D8_D9_M
INM
D6_D7_P
AGND
D6_D7_M
AVDD
D4_D5_P
AGND
D4_D5_M
AVDD
D2_D3_P
AVDD_BUF
D2_D3_M
AVDD
D0_D1_P
RESERVED
D0_D1_M
AVDD
1
2
3
4
5
6
7
8
9
10
11
12
DRGND
DRVDD
OVR_SDOUT
CLKOUTM
CLKOUTP
DFS
OE
AVDD
AGND
CLKP
CLKM
AGND
48 47 46 45 44 43 42
41 40 39 38
13 14 15 16 17 18 19 20 21 22 23
37
24
ADS41B29
ADS41B49
SBAS486E – NOVEMBER 2009–REVISED JULY 2012 www.ti.com
RGZ PACKAGE
(2)
QFN-48
(TOP VIEW)
(2) The PowerPAD™ is connected to DRGND.
Figure 2. ADS41B29 LVDS Pinout
ADS41B49, ADS41B29 Pin Descriptions (LVDS Mode)
# OF
PIN NAME PIN NUMBER PINS FUNCTION DESCRIPTION
AVDD 8, 18, 20, 22, 24, 26 6 I 1.8V analog power supply
AVDD_BUF 21 1 I 3.3V input buffer supply
AGND 9, 12, 14, 17, 19, 25 6 I Analog ground
CLKP 10 1 I Differential clock input, positive
CLKM 11 1 I Differential clock input, negative
INP 15 1 I Differential analog input, positive
INM 16 1 I Differential analog input, negative
Outputs the common-mode voltage that can be used externally to bias the analog
VCM 13 1 O
input pins.
Serial interface RESET input.
When using the serial interface mode, the internal registers must initialize through
hardware RESET by applying a high pulse on this pin or by using the software
RESET 30 1 I reset option; refer to the Serial Interface section.
When RESET is tied high, the internal registers are reset to the default values. In
this condition, SDATA can be used as a control pin.
RESET has an internal 100kΩ pull-down resistor.
This pin functions as a serial interface clock input when RESET is low. When
SCLK 29 1 I RESET is high, SCLK has no function and should be tied to ground. This pin has
an internal 180kΩ pull-down resistor
This pin functions as a serial interface data input when RESET is low. When
SDATA 28 1 I RESET is high, SDATA functions as a STANDBY control pin (see Table 7). This
pin has an internal 180kΩ pull-down resistor.
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Product Folder Link(s): ADS41B29 ADS41B49