Datasheet

CMOSOutputBuffers
14-BitADCData
ADS41Bx9
CLKOUT
D0
D1
D2
D12
D13
CLKIN
D0_In
D1_In
D2_In
D12_In
D13_In
UseExternalClockBuffer
(>200MSPS)
Useshorttracesbetween
ADCoutputandreceiverpins(1to2inches).
Flip-Flops
Receiver(FPGA,ASIC,etc.)
InputClock
ADS41B29
ADS41B49
www.ti.com SBAS486E – NOVEMBER 2009–REVISED JULY 2012
Figure 73. Using the CMOS Data Outputs
CMOS Interface Power Dissipation
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every
output pin. The maximum DRVDD current occurs when each output bit toggles between '0' and '1' every clock
cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined
by the average number of output bits switching, which is a function of the sampling frequency and the nature of
the analog input signal.
Digital Current as a Result of CMOS Output Switching = C
L
× DRVDD × (N × f
AVG
)
where:
C
L
= load capacitance,
N × F
AVG
= average number of output bits switching. (1)
Figure 52 illustrates the current across sampling frequencies at 2MHz analog input frequency.
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