Datasheet

V
DIFF
V
DIFF
1.1V
High
Low
Low
High
OUTP
OUTM
R
OUT
External
100 LoadW
ADS41B29
ADS41B49
www.ti.com SBAS486E – NOVEMBER 2009–REVISED JULY 2012
LVDS Output Data and Clock Buffers
The equivalent circuit of each LVDS output buffer is shown in Figure 71. After reset, the buffer presents an
output impedance of 100Ω to match with the external 100Ω termination.
The V
DIFF
voltage is nominally 350mV, resulting in an output swing of ±350mV with 100Ω external termination.
The V
DIFF
voltage is programmable using the LVDS SWING register bits from ±125mV to ±570mV.
Additionally, a mode exists to double the strength of the LVDS buffer to support 50Ω differential termination. This
mode can be used when the output LVDS signal is routed to two separate receiver chips, each using a 100Ω
termination. The mode can be enabled using the LVDS DATA STRENGTH and LVDS CLKOUT STRENGTH
register bits for data and output clock buffers, respectively.
The buffer output impedance behaves in the same way as a source-side series termination. By absorbing
reflections from the receiver end, it helps to improve signal integrity.
NOTE: Use the default buffer strength to match 100Ω external termination (R
OUT
= 100Ω). To match with a 50Ω external termination, set the
LVDS STRENGTH bit (R
OUT
= 50Ω).
Figure 71. LVDS Buffer Equivalent Circuit
Parallel CMOS Interface
In CMOS mode, each data bit is output on a separate pin as the CMOS voltage level, for every clock cycle. The
rising edge of the output clock CLKOUT can be used to latch data in the receiver. Figure 72 depicts the CMOS
output interface.
Switching noise (caused by CMOS output data transitions) can couple into the analog inputs and degrade SNR.
The coupling and SNR degradation increases as the output buffer drive is made stronger. To minimize this
degradation, the CMOS output buffers are designed with controlled drive strength. The default drive strength
ensures a wide data stable window (even at 250MSPS) is provided so the data outputs have minimal load
capacitance. It is recommended to use short traces (one to two inches or 2,54cm to 5,08cm) terminated with less
than 5pF load capacitance, as shown in Figure 73.
For sampling frequencies greater than 200MSPS, it is recommended to use an external clock to capture data.
The delay from input clock to output data and the data valid times are specified for higher sampling frequencies.
These timings can be used to delay the input clock appropriately and use it to capture data.
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