Datasheet

D10_D11_M
D10_D11_P
D8_D9_M
D8_D9_P
D6_D7_M
D6_D7_P
D4_D5_M
D4_D5_P
D2_D3_M
D2_D3_P
D0_D1_M
D0_D1_P
CLKOUTM
DataBitsD10,D11
DataBitsD8,D9
DataBitsD6,D7
DataBitsD4,D5
DataBitsD2,D3
DataBitsD0,D1
OutputClock
CLKOUTP
Pins
ADS41B49
LVDSBuffers
14-Bit
ADCData
D12_D13_M
D12_D13_P
DataBitsD12,D13
D10_D11_M
D10_D11_P
D8_D9_M
D8_D9_P
D6_D7_M
D6_D7_P
D4_D5_M
D4_D5_P
D2_D3_M
D2_D3_P
D0_D1_M
D0_D1_P
CLKOUTM
DataBitsD10,D11
DataBitsD8,D9
DataBitsD6,D7
DataBitsD4,D5
DataBitsD2,D3
DataBitsD0,D1
OutputClock
CLKOUTP
Pins
ADS41B29
LVDSBuffers
12-Bit
ADCData
ADS41B29
ADS41B49
www.ti.com SBAS486E – NOVEMBER 2009–REVISED JULY 2012
DIGITAL OUTPUT INFORMATION
The ADS41B29/49 provide either 14-bit data or 12-bit data, respectively, and an output clock synchronized with
the data.
Output Interface
Two output interface options are available: double data rate (DDR) LVDS and parallel CMOS. They can be
selected using the LVDS CMOS serial interface register bit or using the DFS pin.
DDR LVDS Outputs
In this mode, the data bits and clock are output using low voltage differential signal (LVDS) levels. Two data bits
are multiplexed and output on each LVDS differential pair, as shown in Figure 68 and Figure 69.
Figure 68. ADS41B29 LVDS Data Outputs
Figure 69. ADS41B49 LVDS Data Outputs
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Product Folder Link(s): ADS41B29 ADS41B49