Datasheet

-5 5
15 25 35
45 55
65
75
85 95 105
Time(ms)
8200
8190
8180
8170
8160
8150
8140
8130
8120
8110
8100
8090
8080
8070
8060
8050
OutputCode(LSB)
OFFSETCORRECTION
TimeResponse
8181
Offsetof
10LSBs
8192
Finalconvergedvalue
Offsetcorrection
convergestooutput
codeof8192
Offsetcorrection
begins
ADS41B29
ADS41B49
SBAS486E – NOVEMBER 2009–REVISED JULY 2012 www.ti.com
After the offset is estimated, the correction can be frozen by setting FREEZE OFFSET CORR = 1. Once frozen,
the last estimated value is used for the offset correction of every clock cycle. Note that offset correction is
disabled by a default after reset.
After a reset, the offset correction is disabled.. To use offset correction set EN OFFSET CORR to '1' and
program the required time constant. Figure 67 shows the time response of the offset correction algorithm after it
is enabled.
Figure 67. Time Response of Offset Correction
POWER DOWN
The ADS41B29/49 has three power-down modes: power-down global, standby, and output buffer disable.
Power-Down Global
In this mode, the entire chip (including the ADC, internal reference, and the output buffers) is powered down,
resulting in reduced total power dissipation of about 7mW. The output buffers are in a high-impedance state. The
wake-up time from the global power-down to data becoming valid in normal mode is typically 100µs. To enter the
global power-down mode, set the PDN GLOBAL register bit.
Standby
In this mode, only the ADC is powered down and the internal references are active, resulting in a fast wake-up
time of 5µs. The total power dissipation in standby mode is approximately 200mW. To enter the standby mode,
set the STBY register bit.
Output Buffer Disable
The output buffers can be disabled and put in a high-impedance state; wakeup time from this mode is fast,
approximately 100ns. This can be controlled using the PDN OBUF register bit or using the OE pin.
Input Clock Stop
In addition, the converter enters a low-power mode when the input clock frequency falls below 1MSPS. The
power dissipation is approximately 92mW.
POWER-SUPPLY SEQUENCE
During power-up, the AVDD, AVDD_BUF, and DRVDD supplies can come up in any sequence. These supplies
are separated in the device. Externally, they can be driven from separate supplies or from a single supply.
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Product Folder Link(s): ADS41B29 ADS41B49