Datasheet

−2.5
−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
2.5
0 2048 4096 6144 8192 10240 12288 14336 16384
Output Code (LSB)
INL (LSB)
35 40 45 50 55 60 65
76
80
84
88
92
69
69.5
70
70.5
71
Input Clock Duty Cycle (%)
THD (dBc)
SNR (dBFS)
THD
SNR
Input Frequency = 10MHz
ADS41B29
ADS41B49
SBAS486E – NOVEMBER 2009–REVISED JULY 2012 www.ti.com
TYPICAL CHARACTERISTICS: ADS41B49 (continued)
At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock,
1.5V
PP
differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
PERFORMANCE ACROSS INPUT CLOCK DUTY CYCLE INTEGRAL NONLINEARITY
Figure 28. Figure 29.
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Product Folder Link(s): ADS41B29 ADS41B49