Datasheet

ADS41B29

ADS41B49

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SBAS486E – NOVEMBER 2009–REVISED JULY 2012

7 6 5 4 3 2 1 0

0 PDN GLOBAL 0 PDN OBUF 0 0 EN LVDS SWING

Bit 0 Always write '0'

Bit 6 PDN GLOBAL: Power-down

This bit sets the state of operation.

0 = Normal operation

1 = Total power down; the ADC, internal references, and output buffers are powered down; slow

wake-up time.

Bit 5 Always write '0'

Bit 4 PDN OBUF: Power-down output buffer

This bit set the output data and clock pins.

0 = Output data and clock pins enabled

1 = Output data and clock pins powered down and put in high- impedance state

Bits[3:2] Always write '0'

Bits[1:0] EN LVDS SWING: LVDS swing control

00 = LVDS swing control using LVDS SWING register bits is disabled

01, 10 = Do not use

11 = LVDS swing control using LVDS SWING register bits is enabled

7 6 5 4 3 2 1 0

HI PERF

0 0 0 0 0 0 0

MODE 2

Bits[7:1] Always write '0'

Bit[0] HI PERF MODE 2: High performance mode 2

This bit is recommended for high input signal frequencies greater than 230MHz.

0 = Default performance after reset

1 = For best performance with high-frequency input signals, set the HIGH PERF MODE 2 bit

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