Datasheet

ADS41B29

ADS41B49

SBAS486E – NOVEMBER 2009–REVISED JULY 2012

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7 6 5 4 3 2 1 0

CLKOUT FALL POSN 0 0 1 STBY 0 0

Bits[7:6] CLKOUT FALL POSN

Controls position of output clock falling edge

LVDS interface:

00 = Default position (timings are specified in this condition)

01 = Setup reduces by 400ps, hold increases by 400ps

10 = Data transition is aligned with rising edge

11 = Setup reduces by 200ps, hold increases by 200ps

CMOS interface:

00 = Default position (timings are specified in this condition)

01 = Falling edge is advanced by 100ps

10 = Falling edge is advanced by 200ps

11 = Falling edge is advanced by 1.5ns

Bits[5:4] Always write '0'

Bit 3 Always write '1'

Bit 2 STBY: Standby mode

This bit sets the standby mode.

0 = Normal operation

1 = Only the ADC and output buffers are powered down; internal reference is active; wake-up time

from standby is fast

Bits[1:0] Always write '0'

Product Folder Link(s): ADS41B29 ADS41B49